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* Skip tied operand pairs that already have the same register.Jakob Stoklund Olesen2012-08-071-10/+11
| | | | llvm-svn: 161454
* Add SelectionDAG::getTargetIndex.Jakob Stoklund Olesen2012-08-074-0/+35
| | | | | | | This adds support for TargetIndex operands during isel. The meaning of these (index, offset, flags) operands is entirely defined by the target. llvm-svn: 161453
* Fix a serious typo in InstCombine's optimization of comparisons.Bob Wilson2012-08-071-1/+1
| | | | | | | | | An unsigned value converted to floating-point will always be greater than a negative constant. Unfortunately InstCombine reversed the check so that unsigned values were being optimized to always be greater than all positive floating-point constants. <rdar://problem/12029145> llvm-svn: 161452
* X86 cmp lowering is looking past truncate on the condition node. It should onlyEvan Cheng2012-08-071-6/+16
| | | | | | | | do so when the high bits are known zero. This caused a subtle miscompilation. rdar://12027825 llvm-svn: 161451
* For non-Darwin platforms, we want to generate stack protectors only forBill Wendling2012-08-071-1/+10
| | | | | | | character arrays. This is in line with what GCC does. <rdar://problem/10529227> llvm-svn: 161446
* Add a new kind of MachineOperand: MO_TargetIndex.Jakob Stoklund Olesen2012-08-071-0/+7
| | | | | | | | | | | | A target index operand looks a lot like a constant pool reference, but it is completely target-defined. It contains the 8-bit TargetFlags, a 32-bit index, and a 64-bit offset. It is preserved by all code generator passes. TargetIndex operands can be used to carry target-specific information in cases where immediate operands won't suffice. llvm-svn: 161441
* Enable lazy compilation in MCJITAndrew Kaylor2012-08-072-13/+55
| | | | llvm-svn: 161438
* Fix a couple of typos.Jakob Stoklund Olesen2012-08-072-2/+2
| | | | llvm-svn: 161437
* Add trace accessor methods, implement primitive if-conversion heuristic.Jakob Stoklund Olesen2012-08-073-15/+78
| | | | | | | | Compare the critical paths of the two traces through an if-conversion candidate. If the difference is larger than the branch brediction penalty, reject the if-conversion. If would never pay. llvm-svn: 161433
* The dominance computation already has logic for computing if an edge dominatesRafael Espindola2012-08-071-27/+40
| | | | | | | | | | | | | | | | | | | | | | | | a use or a BB, but it is inline in the handling of the invoke instruction. This patch refactors it so that it can be used in other cases. For example, in define i32 @f(i32 %x) { bb0: %cmp = icmp eq i32 %x, 0 br i1 %cmp, label %bb2, label %bb1 bb1: br label %bb2 bb2: %cond = phi i32 [ %x, %bb0 ], [ 0, %bb1 ] %foo = add i32 %cond, %x ret i32 %foo } GVN should be able to replace %x with 0 in any use that is dominated by the true edge out of bb0. In the above example the only such use is the one in the phi. llvm-svn: 161429
* Add a comment about mftb vs. mfspr on PPC.Hal Finkel2012-08-071-0/+4
| | | | | | Thanks to Alex Rosenberg for the suggestion. llvm-svn: 161428
* Fix the representation of debug line table in DebugInfo LLVM library,Alexey Samsonov2012-08-073-48/+134
| | | | | | | | | | | | | and "instruction address -> file/line" lookup. Instead of plain collection of rows, debug line table for compilation unit is now treated as the number of row ranges, describing sequences (series of contiguous machine instructions). The sequences are not always listed in the order of increasing address, so previously used std::lower_bound() sometimes produced wrong results. Now the instruction address lookup consists of two stages: finding the correct sequence, and searching for address in range of rows for this sequence. llvm-svn: 161414
* PR13095: Give an inline cost bonus to functions using byval arguments.Benjamin Kramer2012-08-071-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | We give a bonus for every argument because the argument setup is not needed anymore when the function is inlined. With this patch we interpret byval arguments as a compact representation of many arguments. The byval argument setup is implemented in the backend as an inline memcpy, so to model the cost as accurately as possible we take the number of pointer-sized elements in the byval argument and give a bonus of 2 instructions for every one of those. The bonus is capped at 8 elements, which is the number of stores at which the x86 backend switches from an expanded inline memcpy to a real memcpy. It would be better to use the real memcpy threshold from the backend, but it's not available via TargetData. This change brings the performance of c-ray in line with gcc 4.7. The included test case tries to reproduce the c-ray problem to catch regressions for this benchmark early, its performance is dominated by the inline decision of a specific call. This only has a small impact on most code, more on x86 and arm than on x86_64 due to the way the ABI works. When building LLVM for x86 it gives a small inline cost boost to virtually any function using StringRef or STL allocators, but only a 0.01% increase in overall binary size. The size of gcc compiled by clang actually shrunk by a couple bytes with this patch applied, but not significantly. llvm-svn: 161413
* Fix PR13412, a nasty miscompile due to the interleavedChandler Carruth2012-08-071-11/+17
| | | | | | | | | | | | | | | | | | instsimplify+inline strategy. The crux of the problem is that instsimplify was reasonably relying on an invariant that is true within any single function, but is no longer true mid-inline the way we use it. This invariant is that an argument pointer != a local (alloca) pointer. The fix is really light weight though, and allows instsimplify to be resiliant to these situations: when checking the relation ships to function arguments, ensure that the argumets come from the same function. If they come from different functions, then none of these assumptions hold. All credit to Benjamin Kramer for coming up with this clever solution to the problem. llvm-svn: 161410
* Add a much more conservative strategy for aligning branch targets.Chandler Carruth2012-08-071-15/+49
| | | | | | | | | | | | | Previously, MBP essentially aligned every branch target it could. This bloats code quite a bit, especially non-looping code which has no real reason to prefer aligned branch targets so heavily. As Andy said in review, it's still a bit odd to do this without a real cost model, but this at least has much more plausible heuristics. Fixes PR13265. llvm-svn: 161409
* MachineCSE: Update the heuristics for isProfitableToCSE.Manman Ren2012-08-071-0/+23
| | | | | | | | | If the result of a common subexpression is used at all uses of the candidate expression, CSE should not increase the live range of the common subexpression. rdar://11393714 and rdar://11819721 llvm-svn: 161396
* Revert r161371. Removing the 'const' before Type is a "good thing".Bill Wendling2012-08-071-12/+12
| | | | | | | | --- Reverse-merging r161371 into '.': U include/llvm/Target/TargetData.h U lib/Target/TargetData.cpp llvm-svn: 161394
* The define for 64 bit sign extension neglected to Jack Carter2012-08-071-7/+8
| | | | | | | | | | | | | | | | | | | | initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop llvm-svn: 161377
* Constify the Type parameter to some methods (which are const anyway).Bill Wendling2012-08-071-12/+12
| | | | llvm-svn: 161371
* Allow x86 subtargets to use the GenericModel defined in X86Schedule.td.Andrew Trick2012-08-071-3/+3
| | | | | | | | | | | This allows codegen passes to query properties like InstrItins->SchedModel->IssueWidth. It also ensure's that computeOperandLatency returns the X86 defaults for loads and "high latency ops". This should have no significant impact on existing schedulers because X86 defaults happen to be the same as global defaults. llvm-svn: 161370
* Mips relocation R_MIPS_64 relocates a 64 bit double word.Jack Carter2012-08-072-0/+4
| | | | | | | | I hit this in a very large program (spirit.cpp), but have not figured out how to make a small make check test for it. llvm-svn: 161366
* The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64 Jack Carter2012-08-062-14/+10
| | | | | | | | | | were using a class defined for 32 bit instructions and thus the instruction was for addiu instead of daddiu. This was corrected by adding the instruction opcode as a field in the base class to be filled in by the defs. llvm-svn: 161359
* Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.Jack Carter2012-08-064-2/+30
| | | | | | | | | | | | | | These 2 relocations gain access to the highest and the second highest 16 bits of a 64 bit object. R_MIPS_HIGHER %higher(A+S) The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. R_MIPS_HIGHEST %highest(A+S) The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. llvm-svn: 161348
* MFTB on PPC64 should really be encoded using MFSPR.Hal Finkel2012-08-061-2/+2
| | | | | | | | | | | The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! llvm-svn: 161346
* Add support for the OpenBSD for Bitrig.Eric Christopher2012-08-065-9/+14
| | | | | | Patch by David Hill. llvm-svn: 161344
* Remove empty overrides of processFunctionBeforeFrameFinalized().Roman Divacky2012-08-063-10/+0
| | | | llvm-svn: 161328
* Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires ↵Craig Topper2012-08-065-55/+187
| | | | | | custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305. llvm-svn: 161318
* Remove custom inserter for MWAIT. It doesn't do anything that couldn't be ↵Craig Topper2012-08-052-24/+2
| | | | | | represented in a pattern. llvm-svn: 161306
* Use a COPY node instead of an explicit MOVA opcode in the custom insterter ↵Craig Topper2012-08-051-2/+1
| | | | | | for pcmpestrm/pcmpistrm. Allows the register allocator to handle it better and prevent wasted identity moves. llvm-svn: 161305
* Add readcyclecounter lowering on PPC64.Hal Finkel2012-08-042-1/+8
| | | | | | | | On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. llvm-svn: 161302
* Skip impdef regs during eabi save/restore list emission to workaround PR11902Anton Korobeynikov2012-08-041-2/+8
| | | | llvm-svn: 161301
* Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack ↵Anton Korobeynikov2012-08-041-0/+4
| | | | | | | | | stuff (this corresponds by spilling/reloading regs in DTriple / DQuad reg classes). No testcase, found by inspection. llvm-svn: 161300
* Add stack spill / reload instructions for DTriple and DQuad register ↵Anton Korobeynikov2012-08-041-3/+43
| | | | | | | | classes, which were missed for no reason. This fixes PR13377 llvm-svn: 161299
* Postpone the deletion of the old name in StructType::setName to allow using ↵Benjamin Kramer2012-08-041-10/+20
| | | | | | | | a slice of the old name. Fixes PR13522. Add a rudimentary unit test to exercise the behavior. llvm-svn: 161296
* Delete a dead variable.Jakob Stoklund Olesen2012-08-041-12/+0
| | | | | | TwoAddressInstructionPass doesn't remat any more. llvm-svn: 161285
* TwoAddressInstructionPass refactoring: Extract another method.Jakob Stoklund Olesen2012-08-031-121/+134
| | | | llvm-svn: 161284
* Refactor and check "onlyReadsMemory" before optimizing builtins.Bob Wilson2012-08-032-83/+30
| | | | | | | | | This patch is mostly just refactoring a bunch of copy-and-pasted code, but it also adds a check that the call instructions are readnone or readonly. That check was already present for sin, cos, sqrt, log2, and exp2 calls, but it was missing for the rest of the builtins being handled in this code. llvm-svn: 161282
* TwoAddressInstructionPass refactoring: Extract a method.Jakob Stoklund Olesen2012-08-031-48/+60
| | | | | | | No functional change intended, except replacing a DenseMap with a SmallDenseMap which should behave identically. llvm-svn: 161281
* Begin adding support for updating LiveIntervals in TwoAddressInstructionPass.Jakob Stoklund Olesen2012-08-031-0/+23
| | | | | | | This is far from complete, and only changes behavior when the -early-live-intervals flag is passed to llc. llvm-svn: 161273
* 1. Redo mips16 instructions to avoid multiple opcodes for same instruction.Akira Hatanaka2012-08-032-54/+269
| | | | | | | | | Change these to patterns. 2. Add another 16 instructions. Patch by Reed Kotler. llvm-svn: 161272
* Add an experimental -early-live-intervals option.Jakob Stoklund Olesen2012-08-032-0/+10
| | | | | | | | | | This option runs LiveIntervals before TwoAddressInstructionPass which will eventually learn to exploit and update the analysis. Eventually, LiveIntervals will run before PHIElimination, and we can get rid of LiveVariables. llvm-svn: 161270
* Delete merged physreg copies in joinReservedPhysReg().Jakob Stoklund Olesen2012-08-031-0/+5
| | | | | | | Previously, the identity copy would survive through register allocation before it was removed by the rewriter. llvm-svn: 161269
* Try to reduce the compile time impact of r161232.Bob Wilson2012-08-032-43/+59
| | | | | | | | | | | | The previous change caused fast isel to not attempt handling any calls to builtin functions. That included things like "printf" and caused some noticable regressions in compile time. I wanted to avoid having fast isel keep a separate list of functions that had to be kept in sync with what the code in SelectionDAGBuilder.cpp was handling. I've resolved that here by moving the list into TargetLibraryInfo. This is somewhat redundant in SelectionDAGBuilder but it will ensure that we keep things consistent. llvm-svn: 161263
* Fix memcmp code-gen to honor -fno-builtin.Bob Wilson2012-08-031-1/+1
| | | | | | | | | I noticed that SelectionDAGBuilder::visitCall was missing a check for memcmp in TargetLibraryInfo, so that it would use custom code for memcmp calls even with -fno-builtin. I also had to add a new -disable-simplify-libcalls option to llc so that I could write a test for this. llvm-svn: 161262
* Completely eliminate VNInfo flags.Jakob Stoklund Olesen2012-08-032-5/+2
| | | | | | | | The 'unused' state of a value number can be represented as an invalid def SlotIndex. This also exposed code that shouldn't have been looking at unused value VNInfos. llvm-svn: 161258
* Fix a couple of loops that were processing unused value numbers.Jakob Stoklund Olesen2012-08-031-1/+5
| | | | | | | Unused VNInfos should be left alone. Their def SlotIndex doesn't point to anything. llvm-svn: 161257
* Silence unused variable warning in -asserts buildMatt Beaumont-Gay2012-08-031-0/+1
| | | | llvm-svn: 161256
* Eliminate the VNInfo::hasPHIKill() flag.Jakob Stoklund Olesen2012-08-034-32/+2
| | | | | | | | | | The only real user of the flag was removeCopyByCommutingDef(), and it has been switched to LiveIntervals::hasPHIKill(). All the code changed by this patch was only concerned with computing and propagating the flag. llvm-svn: 161255
* Make the hasPHIKills flag a computed property.Jakob Stoklund Olesen2012-08-032-4/+25
| | | | | | | | | | | | | The VNInfo::HAS_PHI_KILL is only half supported. We precompute it in LiveIntervalAnalysis, but it isn't properly updated by live range splitting and functions like shrinkToUses(). It is only used in one place: RegisterCoalescer::removeCopyByCommutingDef(). This patch changes that function to use a new LiveIntervals::hasPHIKill() function that computes the flag for a given value number. llvm-svn: 161254
* Delete dead function.Jakob Stoklund Olesen2012-08-031-28/+0
| | | | llvm-svn: 161242
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