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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-07 22:47:06 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-07 22:47:06 +0000 |
| commit | fbf45dc2bd072e5cab720fff02747913b2e9bd11 (patch) | |
| tree | a3beedd0bff82bb9cd680cacf1ac12fdf6b30e0f /llvm/lib | |
| parent | 505715d816c9314c1ebc89ff70be245ad150377a (diff) | |
| download | bcm5719-llvm-fbf45dc2bd072e5cab720fff02747913b2e9bd11.tar.gz bcm5719-llvm-fbf45dc2bd072e5cab720fff02747913b2e9bd11.zip | |
Skip tied operand pairs that already have the same register.
llvm-svn: 161454
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 62d54208c6d..d22274496ab 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1209,27 +1209,28 @@ collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) { if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) continue; AnyOps = true; + MachineOperand &SrcMO = MI->getOperand(SrcIdx); + MachineOperand &DstMO = MI->getOperand(DstIdx); + unsigned SrcReg = SrcMO.getReg(); + unsigned DstReg = DstMO.getReg(); + // Tied constraint already satisfied? + if (SrcReg == DstReg) + continue; - assert(MI->getOperand(SrcIdx).isReg() && - MI->getOperand(SrcIdx).getReg() && - MI->getOperand(SrcIdx).isUse() && - "two address instruction invalid"); - - unsigned RegB = MI->getOperand(SrcIdx).getReg(); + assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); // Deal with <undef> uses immediately - simply rewrite the src operand. - if (MI->getOperand(SrcIdx).isUndef()) { - unsigned DstReg = MI->getOperand(DstIdx).getReg(); + if (SrcMO.isUndef()) { // Constrain the DstReg register class if required. if (TargetRegisterInfo::isVirtualRegister(DstReg)) if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx, TRI, *MF)) MRI->constrainRegClass(DstReg, RC); - MI->getOperand(SrcIdx).setReg(DstReg); + SrcMO.setReg(DstReg); DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI); continue; } - TiedOperands[RegB].push_back(std::make_pair(SrcIdx, DstIdx)); + TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); } return AnyOps; } |

