summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}Bruno Cardoso Lopes2011-09-031-11/+27
| | | | llvm-svn: 139067
* Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicateBruno Cardoso Lopes2011-09-031-17/+45
| | | | | | | that the AVX versions (even the 128-bit ones) all clear the upper part of the destination register. llvm-svn: 139066
* Enforce subtarget checks in a few places to be explicit when theBruno Cardoso Lopes2011-09-031-29/+33
| | | | | | pattern should be matched llvm-svn: 139065
* Tidy up code moving patterns to their appropriate place!Bruno Cardoso Lopes2011-09-031-111/+94
| | | | llvm-svn: 139064
* Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to useBruno Cardoso Lopes2011-09-032-3/+25
| | | | | | it! llvm-svn: 139063
* Teach X86FastISel to use AVX versions of instructions when possibleBruno Cardoso Lopes2011-09-031-18/+26
| | | | llvm-svn: 139062
* Fix 80-column and styleBruno Cardoso Lopes2011-09-031-51/+51
| | | | llvm-svn: 139061
* Tidy up some SSE/AVX convert intrinsics. Also add an AVX version ofBruno Cardoso Lopes2011-09-031-18/+26
| | | | | | OptForSize pattern llvm-svn: 139060
* Fix a truly heinous bug in DAGCombine related to AssertZext.Owen Anderson2011-09-031-7/+6
| | | | | | | If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert. The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users. No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem. Fixes <rdar://problem/10063365>. llvm-svn: 139059
* Pseudo CMOV instructions don't clobber EFLAGS.Jakob Stoklund Olesen2011-09-021-13/+3
| | | | | | | | | | | | | | The explanation about a 0 argument being materialized as xor is no longer valid. Rematerialization will check if EFLAGS is live before clobbering it. The code produced by X86TargetLowering::EmitLoweredSelect does not clobber EFLAGS. This causes one less testb instruction to be generated in the cmov.ll test case. llvm-svn: 139057
* Check for EFLAGS live-out before clobbering it.Jakob Stoklund Olesen2011-09-021-8/+10
| | | | | | | It is only allowed to clobber EFLAGS at the end of a block if it isn't live-in to any successor. llvm-svn: 139056
* Use existing function.Jakob Stoklund Olesen2011-09-021-7/+3
| | | | llvm-svn: 139055
* Thumb2 parsing and encoding for BXJ.Jim Grosbach2011-09-021-6/+3
| | | | llvm-svn: 139053
* Thumb2 parsing and encoding of B instruction.Jim Grosbach2011-09-021-9/+21
| | | | | | | Tweak handling of IT blocks a bit to enable this. The differentiation between B and Bcc needs special sauce. llvm-svn: 139049
* Remove unused variables.Jakob Stoklund Olesen2011-09-021-4/+0
| | | | llvm-svn: 139047
* Don't fast-isel for atomic load/store; some cases require extra handling ↵Eli Friedman2011-09-022-0/+16
| | | | | | missing from fast-isel. llvm-svn: 139044
* Thumb2 parsing and encoding for ASR.Jim Grosbach2011-09-021-12/+38
| | | | | | | For other shift and rotate instructions, too. Tests for those forthcoming as I work my way through the ISA. llvm-svn: 139040
* Comment and clarifying assert.Andrew Trick2011-09-021-0/+1
| | | | llvm-svn: 139036
* No need to get fancy inserting a PHI node when the values are stored in stackBill Wendling2011-09-021-43/+15
| | | | | | | | slots. This fixes a bug where the number of nodes coming into the PHI node may not equal the number of predecessors. E.g., two or more landingpad instructions may require a PHI before reaching the eh.exception and eh.selector instructions. llvm-svn: 139035
* Change X86 disassembly to print immediates values as signed by default. SpecialKevin Enderby2011-09-022-1/+36
| | | | | | case those instructions that the immediate is not sign-extend. radr://8795217 llvm-svn: 139028
* Tidy up. Formatting.Jim Grosbach2011-09-024-16/+18
| | | | llvm-svn: 139024
* Update comments to reflect reality.Bill Wendling2011-09-022-4/+2
| | | | llvm-svn: 139023
* Tidy up. 80 columns.Jim Grosbach2011-09-021-4/+8
| | | | llvm-svn: 139022
* Thumb2 parsing and encoding for AND (register).Jim Grosbach2011-09-021-1/+21
| | | | llvm-svn: 139021
* Simplify by using isFullCopy().Jakob Stoklund Olesen2011-09-021-3/+1
| | | | llvm-svn: 139019
* Revert r138826 until PR10834 can be fixed.Bill Wendling2011-09-021-1/+8
| | | | llvm-svn: 139018
* Thumb2 parsing and encoding for ADD (register).Jim Grosbach2011-09-021-9/+14
| | | | llvm-svn: 139017
* Darwin wants ctors/dtors to be ordered the other way round to linux.Duncan Sands2011-09-023-1/+12
| | | | llvm-svn: 139015
* Enable SCEV-based unrolling by default.Andrew Trick2011-09-021-3/+3
| | | | | | | | | | | | | | | | | | | | This changes loop unrolling to use the same mechanism for trip count computation as indvars. This is a stronger check that tends to unroll more loops. A very common side-effect is that many single iteration loops will be removed sooner. The real goal was simply to remove dependence on canonical IVs. x86 is break even. ARM performance changes to expect (+ is good): External/SPEC/CFP2000/183.equake/183.equake +13% SingleSource/Benchmarks/Dhrystone/fldry +21% MultiSource/Applications/spiff/spiff +3% SingleSource/Benchmarks/Stanford/Puzzle -14% The Puzzle regression is actually an improvement in loop optimization that defeats GVN: rdar://problem/10065079. llvm-svn: 139009
* Return undef value (instead of arbitrary) for wrong or undef index inJakub Staszak2011-09-021-4/+4
| | | | | | ConstantVector. llvm-svn: 139007
* ConstantVector returns arbitrary value for the wrong index.Jakub Staszak2011-09-021-0/+4
| | | | | | This fixes PR10813. llvm-svn: 139006
* Compare type size instead of type _store_ size to make sure that BitCastInstJakub Staszak2011-09-021-2/+2
| | | | | | will be valid. This fixes PR10820. llvm-svn: 139005
* Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.Kalle Raiskila2011-09-021-2/+2
| | | | llvm-svn: 139004
* Perform the upgrading of the old EH to the new EH in a more sane manner.Bill Wendling2011-09-021-34/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | Perform the upgrading in steps. * First, create a map of the invokes to the EH intrinsics. * Next, take that mapping and determine if the invoke's unwind destination has a single predecessor. If not, then create a new empty block to hold the new landingpad instruction. * Create a landingpad instruction into the uwnind destination. Fill it with the values from the old selector. Map the old intrinsic calls to the new landingpad values (there may be multiple landingpad instructions per instrinic call pairs). * Go through the old intrinsic calls, create a PHI node when necessary, and then replace their values with the new values from the landingpad instructions. * Delete all dead instructions. * ??? * Profit! llvm-svn: 138990
* Merge the ARM disassembler header into the implementation file, since it is ↵Owen Anderson2011-09-012-85/+54
| | | | | | not externally exposed. llvm-svn: 138982
* Fix 80 columns violations.Owen Anderson2011-09-011-449/+655
| | | | llvm-svn: 138980
* Revert r131152, r129796, r129761. This code is currently consideredDan Gohman2011-09-011-52/+43
| | | | | | | | to be unreliable on platforms which require memcpy calls, and it is complicating broader legalize cleanups. It is hoped that these cleanups will make memcpy byval easier to implement in the future. llvm-svn: 138977
* Don't drop alignment info on local common symbols.Benjamin Kramer2011-09-0114-27/+45
| | | | | | | | | | | - On COFF the .lcomm directive has an alignment argument. - On ELF we fall back to .local + .comm Based on a patch by NAKAMURA Takumi. Fixes PR9337, PR9483 and PR10128. llvm-svn: 138976
* Null-initialize to shut up -Wuninitialized warnings.Eli Friedman2011-09-011-1/+1
| | | | llvm-svn: 138974
* Fix apparent build error caused by r138948 on certain versions of GCC with ↵James Molloy2011-09-012-21/+36
| | | | | | -Werror. Sorry for the inconvenience. llvm-svn: 138973
* Reduce indentation. No functionality change.Bill Wendling2011-09-011-17/+18
| | | | llvm-svn: 138968
* Change worklist driven deletion to be an iterative process.Bill Wendling2011-09-012-42/+12
| | | | | | Duncan noticed this! llvm-svn: 138967
* Fix an issue with the IR sink pass found by inspection. (I'm not sure ↵Eli Friedman2011-09-011-7/+6
| | | | | | anyone is actually using this, but might as well fix it since I found the issue.) llvm-svn: 138965
* Fix the build for us -Werror users.Nick Lewycky2011-09-012-37/+24
| | | | | | | Remove broken emacs mode major notation marking a C++ file as C. No functionality change. llvm-svn: 138963
* Make isSafeToSpeculativelyExecute() return the right answer for some new ↵Eli Friedman2011-09-011-0/+4
| | | | | | instructions. Found by inspection; not sure what practical impact, if any, this has. llvm-svn: 138962
* Permit remat of partial register defs when it is safe.Jakob Stoklund Olesen2011-09-011-5/+10
| | | | | | | | | | | | | | | | | An instruction may define part of a register where the other bits are undefined. In that case, it is safe to rematerialize the instruction. For example: %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def> The extra <imp-def> operand indicates that the instruction does not read the other parts of the virtual register, so a remat is safe. This patch simply allows multiple def operands for the virtual register. It is MI->readsVirtualRegister() that determines if we depend on a previous value so remat is impossible. llvm-svn: 138953
* ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.Jim Grosbach2011-09-011-1/+1
| | | | llvm-svn: 138952
* Fix vbroadcast matching logic to early unmatch if the node doesn't haveBruno Cardoso Lopes2011-09-011-1/+5
| | | | | | only one use. Fix PR10825. llvm-svn: 138951
* Fix up r137380 based on post-commit review by Jim Grosbach.James Molloy2011-09-013-612/+627
| | | | llvm-svn: 138948
* t2Bcc is allowed to have a predicate without a preceding IT instruction.Owen Anderson2011-09-011-1/+2
| | | | llvm-svn: 138946
OpenPOWER on IntegriCloud