summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
authorOwen Anderson <resistor@mac.com>2011-09-01 17:47:45 +0000
committerOwen Anderson <resistor@mac.com>2011-09-01 17:47:45 +0000
commit35d240f9e899d5c76528dda413db3943756794d5 (patch)
treed60575ba2a3795d90cf75a9569d700b75e372cad /llvm/lib
parente417273fceb76b266a7d384dba345e3d0c85a898 (diff)
downloadbcm5719-llvm-35d240f9e899d5c76528dda413db3943756794d5.tar.gz
bcm5719-llvm-35d240f9e899d5c76528dda413db3943756794d5.zip
t2Bcc is allowed to have a predicate without a preceding IT instruction.
llvm-svn: 138946
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index bba09d4674b..f71d0f8642c 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -3377,7 +3377,8 @@ validateInstruction(MCInst &Inst,
// Check for non-'al' condition codes outside of the IT block.
} else if (isThumbTwo() && MCID.isPredicable() &&
Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
- ARMCC::AL && Inst.getOpcode() != ARM::tBcc)
+ ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
+ Inst.getOpcode() != ARM::t2Bcc)
return Error(Loc, "predicated instructions must be in IT block");
switch (Inst.getOpcode()) {
OpenPOWER on IntegriCloud