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* [DAG] Move integer setcc %x, %x folding into FoldSetCCSimon Pilgrim2019-03-132-5/+6
| | | | | | | | | | First step towards PR40800 - I intend to move the float case in a separate future patch. I had to tweak the (overly reduced) thumb2 test and the x86 widening test change is annoying (no longer rematerializable) but we should address this separately. Differential Revision: https://reviews.llvm.org/D59244 llvm-svn: 356040
* [MIPS][microMIPS] Fix PseudoMTLOHI_MM matching and expansionSimon Atanasyan2019-03-132-1/+6
| | | | | | | | | | | | | | On micromips MipsMTLOHI is always matched to PseudoMTLOHI_DSP regardless of +dsp argument. This patch checks is HasDSP predicate is present for PseudoMTLOHI_DSP so PseudoMTLOHI_MM can be matched when appropriate. Add expansion of PseudoMTLOHI_MM instruction into a mtlo/mthi pair. Patch by Mirko Brkusanin. Differential Revision: http://reviews.llvm.org/D59203 llvm-svn: 356039
* [ELF] Fix GCC8 warnings about "fall through", NFCIJonas Hahnfeld2019-03-132-0/+10
| | | | | | | | | | | | | | | Add break statements in Object/ELF.cpp since the code should consider the generic tags for Hexagon, MIPS, and PPC. Add a test (copied from llvm-readobj) to show that this works correctly (earlier versions of this patch would have asserted). The warnings in X86ELFObjectWriter.cpp are actually false-positives since the nested switch() handles all possible values and returns in all cases. Make this explicit by adding llvm_unreachable's. Differential Revision: https://reviews.llvm.org/D58837 llvm-svn: 356037
* [Support] Treat truncation of fullpath as errorJonas Hahnfeld2019-03-131-1/+5
| | | | | | | | | | | | If the concatenation of arguments dir and bin has at least PATH_MAX characters the call to snprintf will truncate. The result will usually not exist, but if it does it's actually incorrect to return that the path exists. (Motivated by GCC compiler warning about format truncation.) Differential Revision: https://reviews.llvm.org/D58835 llvm-svn: 356036
* [RISCV] Replace incorrect use of sizeof with array_lengthofAlex Bradbury2019-03-131-3/+3
| | | | | | | RISCVDisassembler was incorrectly using sizeof(Arr) when it should have used sizeof(Arr)/sizeof(Arr[0]). Update to use array_lengthof instead. llvm-svn: 356035
* [ImplicitNullChecks] Support unordered atomic accessesPhilip Reames2019-03-131-5/+2
| | | | | | Update the INC pass to allow folding unordered atomics. This is the first optimization unblocked by the changes landed from D57601. llvm-svn: 356006
* Revert "[llvm] Skip over empty line table entries."Evgeniy Stepanov2019-03-131-7/+0
| | | | | | | This reverts commit r355972. See the discussion at https://reviews.llvm.org/D58952. llvm-svn: 356001
* [X86] Enable printAliasInstr for the Intel assembly printer so that AAM and ↵Craig Topper2019-03-132-1/+9
| | | | | | AAD will print without an immediate when the immediate is 10. llvm-svn: 355997
* [WebAssembly] Place 'try' and 'catch' correctly wrt EH_LABELsHeejin Ahn2019-03-132-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: After instruction selection phase, possibly-throwing calls, which were previously invoke, are wrapped in `EH_LABEL` instructions. For example: ``` EH_LABEL <mcsymbol .Ltmp0> CALL_VOID @foo ... EH_LABEL <mcsymbol .Ltmp1> ``` `EH_LABEL` is placed also in the beginning of EH pads: ``` bb.1 (landing-pad): EH_LABEL <mcsymbol .Ltmp2> ... ``` And we'd like to maintian this relationship, so when we place a `try`, ``` TRY ... EH_LABEL <mcsymbol .Ltmp0> CALL_VOID @foo ... EH_LABEL <mcsymbol .Ltmp1> ``` When we place a `catch`, ``` bb.1 (landing-pad): EH_LABEL <mcsymbol .Ltmp2> %0:except_ref = CATCH ... ... ``` Previously we didn't treat EH_LABELs specially, so `try` was placed right before a call, and `catch` was placed in the beginning of an EH pad. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58914 llvm-svn: 355996
* Use AIX version detection at LLVM run-timeHubert Tong2019-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | | Summary: AIX compilers define macros based on the version of the operating system. This patch implements updating of versionless AIX triples to include the host AIX version. Also, the host triple detection in the build system is adjusted to strip the AIX version information so that the run-time detection is preferred. Reviewers: xingxue, stefanp, nemanjai, jasonliu Reviewed By: xingxue Subscribers: mgorny, kristina, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58798 llvm-svn: 355995
* Add XCOFF triple object format type for AIXJason Liu2019-03-125-0/+21
| | | | | | | | | This patch adds an XCOFF triple object format type into LLVM. This XCOFF triple object file type will be used later by object file and assembly generation for the AIX platform. Differential Revision: https://reviews.llvm.org/D58930 llvm-svn: 355989
* Reland "[Remarks] Add -foptimization-record-passes to filter remark emission"Francis Visoiu Mistrih2019-03-125-5/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently we have -Rpass for filtering the remarks that are displayed as diagnostics, but when using -fsave-optimization-record, there is no way to filter the remarks while generating them. This adds support for filtering remarks by passes using a regex. Ex: `clang -fsave-optimization-record -foptimization-record-passes=inline` will only emit the remarks coming from the pass `inline`. This adds: * `-fsave-optimization-record` to the driver * `-opt-record-passes` to cc1 * `-lto-pass-remarks-filter` to the LTOCodeGenerator * `--opt-remarks-passes` to lld * `-pass-remarks-filter` to llc, opt, llvm-lto, llvm-lto2 * `-opt-remarks-passes` to gold-plugin Differential Revision: https://reviews.llvm.org/D59268 Original llvm-svn: 355964 llvm-svn: 355984
* For faulting ops, include a comment w/the fault destinationPhilip Reames2019-03-121-0/+1
| | | | | | A faulting_op is one that has specified behavior when a fault occurs, generally redirecting control flow to another location. This change just adds a comment to the assembly output which makes it both human readable, and machine checkable w/o having to parse the FaultMap section. This is used to split a test file into two parts, so that I can (in a near future commit) easily extend the test file to demonstrate another case. llvm-svn: 355982
* IR: Add immarg attributeMatt Arsenault2019-03-1211-117/+85
| | | | | | | | | | | | | | | | | This indicates an intrinsic parameter is required to be a constant, and should not be replaced with a non-constant value. Add the attribute to all AMDGPU and generic intrinsics that comments indicate it should apply to. I scanned other target intrinsics, but I don't see any obvious comments indicating which arguments are intended to be only immediates. This breaks one questionable testcase for the autoupgrade. I'm unclear on whether the autoupgrade is supposed to really handle declarations which were never valid. The verifier fails because the attributes now refer to a parameter past the end of the argument list. llvm-svn: 355981
* Revert "[Remarks] Add -foptimization-record-passes to filter remark emission"Francis Visoiu Mistrih2019-03-125-35/+5
| | | | | | This reverts commit 20fff32b7d1f1a1bd417b22aa9f26ededd97a3e5. llvm-svn: 355976
* [llvm] Skip over empty line table entries.Mircea Trofin2019-03-121-0/+7
| | | | | | | | | | | | | | | | | | Summary: This is similar to how addr2line handles consecutive entries with the same address - pick the last one. Reviewers: dblaikie, friss, JDevlieghere Reviewed By: dblaikie Subscribers: ormris, echristo, JDevlieghere, probinson, aprantl, hiraditya, rupprecht, jdoerfert, llvm-commits Tags: #llvm, #debug-info Differential Revision: https://reviews.llvm.org/D58952 llvm-svn: 355972
* MIR: Stop reinitializing target information for every useMatt Arsenault2019-03-123-327/+378
| | | | | | | | | | | | | | | Every time a physical register reference was parsed, this would initialize a string map for every register in in target, and discard it for the next. The same applies for the other fields initialized from target information. Follow along with how the function state is tracked, and add a new tracking class for target information. The string->register class/register bank for some reason were kept separately, so track them in the same place. llvm-svn: 355970
* [Remarks] Add -foptimization-record-passes to filter remark emissionFrancis Visoiu Mistrih2019-03-125-5/+35
| | | | | | | | | | | | | | | | | | | | | | | | Currently we have -Rpass for filtering the remarks that are displayed as diagnostics, but when using -fsave-optimization-record, there is no way to filter the remarks while generating them. This adds support for filtering remarks by passes using a regex. Ex: `clang -fsave-optimization-record -foptimization-record-passes=inline` will only emit the remarks coming from the pass `inline`. This adds: * `-fsave-optimization-record` to the driver * `-opt-record-passes` to cc1 * `-lto-pass-remarks-filter` to the LTOCodeGenerator * `--opt-remarks-passes` to lld * `-pass-remarks-filter` to llc, opt, llvm-lto, llvm-lto2 * `-opt-remarks-passes` to gold-plugin Differential Revision: https://reviews.llvm.org/D59268 llvm-svn: 355964
* [SROA] Fix a crash when trying to convert a memset to an non-integral ↵Philip Reames2019-03-121-6/+17
| | | | | | | | | | | | pointer type The included test case currently crashes on tip of tree. Rather than adding a bailout, I chose to restructure the code so that the existing helper function could be used. Given that, the majority of the diff is NFC-ish, but the key difference is that canConvertValue returns false when only one side is a non-integral pointer. Thanks to Cherry Zhang for the test case. Differential Revision: https://reviews.llvm.org/D59000 llvm-svn: 355962
* [x86] scalarize extractelement 0 of FP vselectSanjay Patel2019-03-121-0/+18
| | | | llvm-svn: 355955
* [CodeGen] Add MMOs to statepoint nodes during SelectionDAGPhilip Reames2019-03-122-22/+51
| | | | | | | | | | | | The existing statepoint lowering code does something odd; it adds machine memory operands post instruction selection. This was copied from the stackmap/patchpoint implementation, but appears to be non-idiomatic. This change is largely NFC. It moves the MMO creation logic into SelectionDAG building. It ends up not quite being NFC because the size of the stack slot is reflected in the MMO. The old code blindly used pointer size for the MMO size, which appears to have always been incorrect for larger values. It just happened nothing actually relied on the MMOs, so it worked out okay. For context, I'm planning on removing the MOVolatile flag from these in a future commit, and then removing the MOStore flag from deopt spill slots in a separate one. Doing so is motivated by a small test case where we should be able to better schedule spill slots, but don't do so due to a memory use/def implied by the statepoint. Differential Revision: https://reviews.llvm.org/D59106 llvm-svn: 355953
* [SCEV] Use depth limit for trunc analysisTeresa Johnson2019-03-121-29/+36
| | | | | | | | | | | | | | | | | | | Summary: This fixes an extremely long compile time caused by recursive analysis of truncs, which were not previously subject to any depth limits unlike some of the other ops. I decided to use the same control used for sext/zext, since the routines analyzing these are sometimes mutually recursive with the trunc analysis. Reviewers: mkazantsev, sanjoy Subscribers: sanjoy, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58994 llvm-svn: 355949
* Set useful flags for vector imm setting instructionsJinsong Ji2019-03-123-5/+16
| | | | | | | | | | | | Vector imm setting instructions like XXLXORz/XXLXORspz/XXLXORdpz Should behave like LI8. We should set corresponding flags to allow rematerialization and other opts in LICM, RA, Scheduling etc. Differential Revision: https://reviews.llvm.org/D58645 llvm-svn: 355948
* [SanitizerCoverage] Avoid splitting critical edges when destination is a ↵Craig Topper2019-03-122-1/+5
| | | | | | | | | | | | basic block containing unreachable This patch adds a new option to SplitAllCriticalEdges and uses it to avoid splitting critical edges when the destination basic block ends with unreachable. Otherwise if we split the critical edge, sanitizer coverage will instrument the new block that gets inserted for the split. But since this block itself shouldn't be reachable this is pointless. These basic blocks will stick around and generate assembly, but they don't end in sane control flow and might get placed at the end of the function. This makes it look like one function has code that flows into the next function. This showed up while compiling the linux kernel with clang. The kernel has a tool called objtool that detected the code that appeared to flow from one function to the next. https://github.com/ClangBuiltLinux/linux/issues/351#issuecomment-461698884 Differential Revision: https://reviews.llvm.org/D57982 llvm-svn: 355947
* [RISCV][MC] Find matching pcrel_hi fixup in more cases.Eli Friedman2019-03-121-4/+12
| | | | | | | | | | | | | | | | | If a symbol points to the end of a fragment, instead of searching for fixups in that fragment, search in the next fragment. Fixes spurious assembler error with subtarget change next to "la" pseudo-instruction, or expanded equivalent. Alternate proposal to fix the problem discussed in https://reviews.llvm.org/D58759. Testcase by Ana Pazos. Differential Revision: https://reviews.llvm.org/D58943 llvm-svn: 355946
* [SDAG] Expand pow2 mulo using shiftsNikita Popov2019-03-121-4/+23
| | | | | | | | | | | Expand MULO with constant power of two operand into a shift. The overflow is checked with (x << shift) >> shift == x, where the right shift will be logical for umulo and arithmetic for smulo (with exception for multiplications by signed_min). Differential Revision: https://reviews.llvm.org/D59041 llvm-svn: 355937
* [X86] Arrange more CPU features to inherit from earlier CPUs. NFCICraig Topper2019-03-121-275/+173
| | | | | | | | This makes SandyBridge inherit back to Westmere/Nehalem. Make bdver1-4 inherit from each other and btver2 inherit from btver1. llvm-svn: 355935
* [DAGCombine] Pull out repeated demanded bitmask generation. NFCI.Simon Pilgrim2019-03-121-10/+9
| | | | llvm-svn: 355932
* [FileCheck]Remove assertions that prevent matching an empty string at file ↵James Henderson2019-03-121-12/+0
| | | | | | | | | | | | | | | | | | | | | | start before CHECK-NEXT/SAME This patch removes two assertions that were preventing writing of a test that checked an empty line followed by some text. For example: CHECK: {{^$}} CHECK-NEXT: foo() The assertion was because the current location the CHECK-NEXT was scanning from was the start of the buffer. A similar issue occurred with CHECK-SAME. These assertions don't protect against anything, as there is already an error check that checks that CHECK-NEXT/EMPTY/SAME don't appear first in the checks, and the following code works fine if the pointer is at the start of the input. Reviewed by: probinson, thopre, jdenny Differential Revision: https://reviews.llvm.org/D58784 llvm-svn: 355928
* CodeGenPrep: preserve inbounds attribute when sinking GEPs.Tim Northover2019-03-121-3/+27
| | | | | | | | | Targets can potentially emit more efficient code if they know address computations never overflow. For example ILP32 code on AArch64 (which only has 64-bit address computation) can ignore the possibility of overflow with this extra information. llvm-svn: 355926
* [format] \t => ' 'Liang Zou2019-03-121-1/+1
| | | | | | | | | | | | | | | | | | Summary: 1. \t => ' ' 2. test commit access Reviewers: Higuoxing, liangdzou Reviewed By: Higuoxing, liangdzou Subscribers: kristina, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59243 llvm-svn: 355924
* [SimplifyLibCalls] Simplify optimizePutsFangrui Song2019-03-121-10/+6
| | | | | | | | | | | The code might intend to replace puts("") with putchar('\n') even if the return value is used. It failed because use_empty() was used to guard the whole block. While returning '\n' (putchar('\n')) is technically correct (puts is only required to return a nonnegative number on success), doing this looks weird and there is really little benefit to optimize puts whose return value is used. So don't do that. llvm-svn: 355921
* [NFC][PowerPC]Assert when trying to generate directmove below P8.Jinsong Ji2019-03-121-1/+4
| | | | | | | | | | | | This was found when we generated COPY from G8RC to F8RC in EmitInstrWithCustomInserter without checking proper architecture, we silently generated mtvsrd, which require P8 and up. This is a NFC patch to add assert when we call copyPhysReg, in case someone accidentally generate COPY between G8RC to F8RC for P7 and below. llvm-svn: 355920
* Revert rL355906: [SLP] Remove redundancy of performing operand reordering ↵Simon Pilgrim2019-03-121-169/+82
| | | | | | | | | | | | | | | | | | twice: once in buildTree() and later in vectorizeTree(). This is a refactoring patch that removes the redundancy of performing operand reordering twice, once in buildTree() and later in vectorizeTree(). To achieve this we need to keep track of the operands within the TreeEntry struct while building the tree, and later in vectorizeTree() we are just accessing them from the TreeEntry in the right order. This patch is the first in a series of patches that will allow for better operand reordering across chains of instructions (e.g., a chain of ADDs), as presented here: https://www.youtube.com/watch?v=gIEn34LvyNo Patch by: @vporpo (Vasileios Porpodas) Differential Revision: https://reviews.llvm.org/D59059 ........ Reverted due to buildbot failures that I don't have time to track down. llvm-svn: 355913
* Try to fix SLPVectorizer BoUpSLP::BoEdgeInfo::dump visibility on non-debug ↵Simon Pilgrim2019-03-121-3/+1
| | | | | | builds llvm-svn: 355912
* [SLP] Remove redundancy of performing operand reordering twice: once in ↵Simon Pilgrim2019-03-121-82/+171
| | | | | | | | | | | | | | | buildTree() and later in vectorizeTree(). This is a refactoring patch that removes the redundancy of performing operand reordering twice, once in buildTree() and later in vectorizeTree(). To achieve this we need to keep track of the operands within the TreeEntry struct while building the tree, and later in vectorizeTree() we are just accessing them from the TreeEntry in the right order. This patch is the first in a series of patches that will allow for better operand reordering across chains of instructions (e.g., a chain of ADDs), as presented here: https://www.youtube.com/watch?v=gIEn34LvyNo Patch by: @vporpo (Vasileios Porpodas) Differential Revision: https://reviews.llvm.org/D59059 llvm-svn: 355906
* [SimplifyLibCalls] Fix comments about fputs, memchr, and s[n]printf. NFCFangrui Song2019-03-121-5/+7
| | | | llvm-svn: 355905
* [CGP] Fix UB when GEP is bound to trivial PHINodeEugene Leviant2019-03-121-0/+1
| | | | | | Differential revision: https://reviews.llvm.org/D59140 llvm-svn: 355904
* [AMDGPU] Add support for immediate operand for S_ENDPGMDavid Stuttard2019-03-129-10/+81
| | | | | | | | | | | | | | | | | Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
* [TTI] Enable analysis of clib functions in getIntrinsicCosts. NFCI.Sjoerd Meijer2019-03-121-6/+9
| | | | | | | | | | | | | | | | | This is addressing the issue that we're not modeling the cost of clib functions in TTI::getIntrinsicCosts and thus we're basically addressing this fixme: // FIXME: This is wrong for libc intrinsics. To enable analysis of clib functions, we not only need an intrinsic ID and formal arguments, but also the actual user of that function so that we can e.g. look at alignment and values of arguments. So, this is the initial plumbing to pass the user of an intrinsinsic on to getCallCosts, which queries getIntrinsicCosts. Differential Revision: https://reviews.llvm.org/D59014 llvm-svn: 355901
* [TableGen] Allow 2^63-1 and 2^63-2 as int literals.Simon Tatham2019-03-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | These two values correspond to the 'Empty' and 'Tombstone' special keys defined by DenseMapInfo<int64_t>, which means that neither one can be used as a key in DenseMap<int64_t, anything>. Hence, if you try to use either of those values as an int literal, IntInit::get() fails an assertion when it tries to insert them into its static cache of int-literal objects. Fixed by replacing the DenseMap with a std::map, which doesn't intrude on the space of legal values of the key type. Reviewers: nhaehnle, hfinkel, javedabsar, efriedma Reviewed By: efriedma Subscribers: fhahn, efriedma, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59016 llvm-svn: 355900
* Very minor typo. NFCKristina Brooks2019-03-121-1/+1
| | | | | | | | | | Typo `we we're` => `we were` in the pass EarlyCSE Patch by liangdzou (Liang ZOU) Differential Revision: https://reviews.llvm.org/D59241 llvm-svn: 355895
* Reland "Relax constraints for reduction vectorization"Sanjoy Das2019-03-125-30/+49
| | | | | | | | | | | | | | | | | | | | | Change from original commit: move test (that uses an X86 triple) into the X86 subdirectory. Original description: Gating vectorizing reductions on *all* fastmath flags seems unnecessary; `reassoc` should be sufficient. Reviewers: tvvikram, mkuper, kristof.beyls, sdesmalen, Ayal Reviewed By: sdesmalen Subscribers: dcaballe, huntergr, jmolloy, mcrosier, jlebar, bixia, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57728 llvm-svn: 355889
* Add Swift enumerator value for CodeView::SourceLanguageNathan Lanza2019-03-114-5/+9
| | | | | | | | | | | | | | | Summary: Swift now generates PDBs for debugging on Windows. llvm and lldb need a language enumerator value too properly handle the output emitted by swiftc. Subscribers: jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59231 llvm-svn: 355882
* Hexagon RDF: Replace function template (plus explicit specializations) with ↵David Blaikie2019-03-114-25/+27
| | | | | | | | | | | | | | | | | | | non-template overloads For the design in question, overloads seem to be a much simpler and less subtle solution. This removes ODR issues, and errors of the kind where code that uses the specialization in question will accidentally and erroneously specialize the primary template. This only "works" by accident; the program is ill-formed NDR. (Found with -Wundefined-func-template.) Patch by Thomas Köppe! Differential Revision: https://reviews.llvm.org/D58998 llvm-svn: 355880
* Revert "Relax constraints for reduction vectorization"Sanjoy Das2019-03-115-49/+30
| | | | | | This reverts commit r355868. Breaks hexagon. llvm-svn: 355873
* [X86] Remove ProcModel and ProcFeatures tablegen classes. Move all feature ↵Craig Topper2019-03-111-392/+380
| | | | | | | | | | | | | | | | | | lists into a ProcessorFeatures class. ProcFeatures was a class that just concatenated two feature lists together and gave it a name. We used it to inherit features between CPUs. ProcModel took a two CPU feature lists and concatenated them before deferring to ProcessorModel. This was to allow inherited features and specific features to be passed to each CPU. Both of these allowed for only very rigid CPU inheritance rules. With this patch we now store all of the lists we were using for inheritance in one object and do any list oncatenation we want there. Then we just pass whatever list we want from this class into the ProcessorModel class for each CPU. Hopefully this gives us more flexibility to build up feature lists in whatever ways we think make sense. Perhaps untangling ISA flags and tuning flags. I've only touched the CPUs that were directly affected by the removal of the ProcModel and ProcFeatures classes. We should move more of the feature lists into ProcessorFeatures. llvm-svn: 355872
* Recommit "[GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT"Jessica Paquette2019-03-113-18/+146
| | | | | | | | | After r355865, we should be able to safely select G_EXTRACT_VECTOR_ELT without running into any problematic intrinsics. Also add a fix for lane copies, which don't support index 0. llvm-svn: 355871
* Remove ASan asm instrumentation.Evgeniy Stepanov2019-03-116-1181/+7
| | | | | | | | | | | | | | Summary: It is incomplete and has no users AFAIK. Reviewers: pcc, vitalybuka Subscribers: srhines, kubamracek, mgorny, krytarowski, eraman, hiraditya, jdoerfert, #sanitizers, llvm-commits, thakis Tags: #sanitizers, #llvm Differential Revision: https://reviews.llvm.org/D59154 llvm-svn: 355870
* [RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64AAlex Bradbury2019-03-111-0/+4
| | | | | | | | | | | | | | | | AtomicCmpSwapWithSuccess is legalised into an AtomicCmpSwap plus a comparison. This requires an extension of the value which, by default, is a zero-extension. When we later lower AtomicCmpSwap into a PseudoCmpXchg32 and then expanded in RISCVExpandPseudoInsts.cpp, the lr.w instruction does a sign-extension. This mismatch of extensions causes the comparison to fail when the compared value is negative. This change overrides TargetLowering::getExtendForAtomicOps for RISC-V so it does a sign-extension instead. Differential Revision: https://reviews.llvm.org/D58829 Patch by Ferran Pallarès Roca. llvm-svn: 355869
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