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| author | Jinsong Ji <jji@us.ibm.com> | 2019-03-12 18:27:09 +0000 |
|---|---|---|
| committer | Jinsong Ji <jji@us.ibm.com> | 2019-03-12 18:27:09 +0000 |
| commit | 9dc2c1d564b25e82a002e312ed9d543637aae027 (patch) | |
| tree | c4b8c2374d277f0c1ca8f62c0218074aadd0e2a1 /llvm/lib | |
| parent | 03e93f514a54d7f1805936ddc0ddbf265d697522 (diff) | |
| download | bcm5719-llvm-9dc2c1d564b25e82a002e312ed9d543637aae027.tar.gz bcm5719-llvm-9dc2c1d564b25e82a002e312ed9d543637aae027.zip | |
Set useful flags for vector imm setting instructions
Vector imm setting instructions like XXLXORz/XXLXORspz/XXLXORdpz
Should behave like LI8.
We should set corresponding flags to allow rematerialization and other
opts in LICM, RA, Scheduling etc.
Differential Revision: https://reviews.llvm.org/D58645
llvm-svn: 355948
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 8 |
3 files changed, 16 insertions, 5 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index f34cea0babe..ae362ff3cc6 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -821,7 +821,9 @@ def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; -let isCodeGenOnly = 1 in { +let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, + isReMaterializable = 1 in { + def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), "vxor $vD, $vD, $vD", IIC_VecFP, [(set v16i8:$vD, (v16i8 immAllZerosV))]>; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 2514e5b87a7..a03742d7402 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -332,6 +332,15 @@ bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI, case PPC::ADDIStocHA: case PPC::ADDItocL: case PPC::LOAD_STACK_GUARD: + case PPC::XXLXORz: + case PPC::XXLXORspz: + case PPC::XXLXORdpz: + case PPC::V_SET0B: + case PPC::V_SET0H: + case PPC::V_SET0: + case PPC::V_SETALLONESB: + case PPC::V_SETALLONESH: + case PPC::V_SETALLONES: return true; } return false; diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 8ca2e04835a..285b4f74e8c 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -840,12 +840,12 @@ let Uses = [RM] in { "xxlxor $XT, $XA, $XB", IIC_VecGeneral, [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>; } // isCommutable - let isCodeGenOnly = 1 in - def XXLXORz : XX3Form_Zero<60, 154, (outs vsrc:$XT), (ins), + + let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, + isReMaterializable = 1 in { + def XXLXORz : XX3Form_Zero<60, 154, (outs vsrc:$XT), (ins), "xxlxor $XT, $XT, $XT", IIC_VecGeneral, [(set v4i32:$XT, (v4i32 immAllZerosV))]>; - - let isCodeGenOnly = 1 in { def XXLXORdpz : XX3Form_SetZero<60, 154, (outs vsfrc:$XT), (ins), "xxlxor $XT, $XT, $XT", IIC_VecGeneral, |
