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llvm-svn: 118192
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element size. Instead,
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
llvm-svn: 118183
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llvm-svn: 118176
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For NEON we had been assuming this was always an immediate constant.
llvm-svn: 118175
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Makes it more clear that it is just a path manipulation function.
llvm-svn: 118174
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the code more self-documenting.
llvm-svn: 118171
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with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
llvm-svn: 118169
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value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
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this by using an undef as a pointer.
Fixes rdar://8625016
llvm-svn: 118164
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extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
llvm-svn: 118160
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llvm-svn: 118152
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llvm-svn: 118151
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easier to read.
llvm-svn: 118148
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
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encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.
llvm-svn: 118143
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llvm-svn: 118141
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printOperand() asm printer helper functions. rdar://8425198
llvm-svn: 118140
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llvm-svn: 118139
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
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1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
llvm-svn: 118135
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latencies) of loads.
llvm-svn: 118134
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llvm-svn: 118130
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llvm-svn: 118128
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llvm-svn: 118127
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llvm-svn: 118126
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instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.
llvm-svn: 118125
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llvm-svn: 118121
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ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
llvm-svn: 118119
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threshold given to createFunctionInliningPass().
Both opt -O3 and clang would silently ignore the -inline-threshold option.
llvm-svn: 118117
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limits on their own.
llvm-svn: 118113
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llvm-svn: 118110
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llvm-svn: 118106
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llvm-svn: 118105
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llvm-svn: 118103
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llvm-svn: 118102
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llvm-svn: 118099
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is handled with the MC encoder.
llvm-svn: 118098
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them to something with semantic meaning.
llvm-svn: 118097
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llvm-svn: 118096
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with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
llvm-svn: 118094
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llvm-svn: 118093
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llvm-svn: 118092
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Additionally, move the implementation of appendSuffix to Path.cpp: it is
platform-independent.
llvm-svn: 118089
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llvm-svn: 118088
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generate.
llvm-svn: 118087
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llvm-svn: 118086
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llvm-svn: 118084
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llvm-svn: 118082
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// FIXME: We should compute this sooner, we don't want to recurse here, and
// we would like to be more functional.
In MCAssembler::ComputeFragmentSize.
llvm-svn: 118080
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llvm-svn: 118069
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