per a suggestion by Frits van Bommel, mark all MBlaze Pseudo

instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.

llvm-svn: 118125

3 files changed, 8 insertions, 5 deletions

diff --git a/llvm/lib/Target/MBlaze/MBlazeInstrFPU.td b/llvm/lib/Target/MBlaze/MBlazeInstrFPU.td
index d264a098134..a26011db4a3 100644
--- a/llvm/lib/Target/MBlaze/MBlazeInstrFPU.td
+++ b/llvm/lib/Target/MBlaze/MBlazeInstrFPU.td
@@ -124,7 +124,7 @@ let isAsCheapAsAMove = 1 in {
 }
 
 
-let usesCustomInserter = 1, isCodeGenOnly = 1 in {
+let usesCustomInserter = 1 in {
   def Select_FCC : MBlazePseudo<(outs GPR:$dst),
     (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC),
     "; SELECT_FCC PSEUDO!",
diff --git a/llvm/lib/Target/MBlaze/MBlazeInstrFormats.td b/llvm/lib/Target/MBlaze/MBlazeInstrFormats.td
index 71e3b12e8e3..8cd330b87f0 100644
--- a/llvm/lib/Target/MBlaze/MBlazeInstrFormats.td
+++ b/llvm/lib/Target/MBlaze/MBlazeInstrFormats.td
@@ -49,8 +49,7 @@ def FC      : Format<18>; // NOP
 
 // Generic MBlaze Format
 class MBlazeInst<bits<6> op, Format form, dag outs, dag ins, string asmstr, 
-                 list<dag> pattern, InstrItinClass itin> : Instruction 
-{
+                 list<dag> pattern, InstrItinClass itin> : Instruction {
   let Namespace = "MBlaze";
   field bits<32> Inst;
 
@@ -61,6 +60,10 @@ class MBlazeInst<bits<6> op, Format form, dag outs, dag ins, string asmstr,
   // Top 6 bits are the 'opcode' field
   let Inst{0-5} = opcode;   
   
+  // If the instruction is marked as a pseudo, set isCodeGenOnly so that the
+  // assembler and disassmbler ignore it.
+  let isCodeGenOnly = !eq(!cast<string>(form), "FPseudo");
+  
   dag OutOperandList = outs;
   dag InOperandList  = ins;
 
diff --git a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td
index d7bb4a3b0ac..c57c1ce04a7 100644
--- a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td
+++ b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td
@@ -125,7 +125,7 @@ def xaddr : ComplexPattern<i32, 2, "SelectAddrRegReg", [], []>;
 //===----------------------------------------------------------------------===//
 
 // As stack alignment is always done with addiu, we need a 16-bit immediate
-let Defs = [R1], Uses = [R1], isCodeGenOnly = 1 in {
+let Defs = [R1], Uses = [R1] in {
 def ADJCALLSTACKDOWN : MBlazePseudo<(outs), (ins simm16:$amt),
                                   "#ADJCALLSTACKDOWN $amt",
                                   [(callseq_start timm:$amt)]>;
@@ -526,7 +526,7 @@ let neverHasSideEffects = 1 in {
   def NOP :  MBlazeInst< 0x20, FC, (outs), (ins), "nop    ", [], IIAlu>;
 }
 
-let usesCustomInserter = 1, isCodeGenOnly = 1 in {
+let usesCustomInserter = 1 in {
   def Select_CC : MBlazePseudo<(outs GPR:$dst),
     (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC),
     "; SELECT_CC PSEUDO!",