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* Add the body of 'visitLandingPad'.Bill Wendling2011-08-171-3/+39
| | | | | | | | This generates the SDNodes for the new exception handling scheme. It takes the two values coming from the landingpad instruction and assigns them to the EXCEPTIONADDR and EHSELECTION nodes. llvm-svn: 137873
* Increment the insertion iterator to beyond the landingpad instruction.Bill Wendling2011-08-171-1/+1
| | | | llvm-svn: 137872
* Don't optimize the landing pad exit block.Bill Wendling2011-08-171-4/+18
| | | | | | | | One way to exit the loop is through an unwind edge. However, that may involve splitting the critical edge of the landing pad, which is non-trivial. Prevent the transformation from rewriting the landing pad exit loop block. llvm-svn: 137871
* Assert that we aren't trying to split the critical edge of a landing pad. DoingBill Wendling2011-08-171-0/+5
| | | | | | so requires more care than this generic algorithm should handle. llvm-svn: 137866
* Fix predicate for imm1_32Jim Grosbach2011-08-171-1/+4
| | | | llvm-svn: 137865
* Thumb assembly parsing and encoding for ADR.Jim Grosbach2011-08-171-1/+1
| | | | llvm-svn: 137864
* Revert r137655. There is some question about whether the 'landingpad'Bill Wendling2011-08-173-3/+5
| | | | | | instruction should be marked as potentially reading and/or writing memory. llvm-svn: 137863
* 80 columns.Jim Grosbach2011-08-171-1/+2
| | | | llvm-svn: 137857
* Tidy up.Jim Grosbach2011-08-171-2/+1
| | | | llvm-svn: 137856
* Modify for the new EH scheme.Bill Wendling2011-08-171-1/+57
| | | | | | | | Things are much saner now. We no longer need to modify the laning pads, because of the invariants we impose upon them. The only thing DwarfEHPrepare needs to do is convert the 'resume' instruction into a call to '_Unwind_Resume'. llvm-svn: 137855
* Revert r137781; I agree with Duncan's comment that the situation in question ↵Eli Friedman2011-08-171-5/+4
| | | | | | is clearly impossible given the current structure of the code. llvm-svn: 137853
* Add support for half-word unaligned loads and stores.Akira Hatanaka2011-08-173-14/+31
| | | | llvm-svn: 137848
* Static fields require an out-of-line definition. Fix DynamicLibrary for real.Jordy Rose2011-08-171-0/+2
| | | | llvm-svn: 137844
* Be more careful in the Thumb decoder hooks to avoid walking off the end of ↵Owen Anderson2011-08-171-8/+12
| | | | | | the OpInfo array. llvm-svn: 137838
* Silly mistake from r137777; restore significant isStructTy() checks. While ↵Eli Friedman2011-08-171-4/+19
| | | | | | | | | | here, be a bit more defensive with unknown instructions. Fixes PR10687. llvm-svn: 137836
* Move pattern matching for EXT and INS to post-legalization DAGCombine per ↵Akira Hatanaka2011-08-172-98/+102
| | | | | | Bruno's comment. llvm-svn: 137831
* Allow the MCDisassembler to return a "soft fail" status code, indicating an ↵Owen Anderson2011-08-176-630/+698
| | | | | | | | instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. Patch by James Molloy. llvm-svn: 137830
* Introduce matching patterns for vbroadcast AVX instruction. The idea is toBruno Cardoso Lopes2011-08-174-0/+66
| | | | | | | | | | | | | match splats in the form (splat (scalar_to_vector (load ...))) whenever the load can be folded. All the logic and instruction emission is working but because of PR8156, there are no ways to match loads, cause they can never be folded for splats. Thus, the tests are XFAILed, but I've tested and exercised all the logic using a relaxed version for checking the foldable loads, as if the bug was already fixed. This should work out of the box once PR8156 gets fixed since MayFoldLoad will work as expected. llvm-svn: 137810
* Update comments about vector splat handling in x86Bruno Cardoso Lopes2011-08-171-8/+7
| | | | llvm-svn: 137808
* Now that we have a canonical way to handle 256-bit splats:Bruno Cardoso Lopes2011-08-171-38/+0
| | | | | | | | | vinsertf128 $1 + vpermilps $0, remove the old code that used to first do the splat in a 128-bit vector and then insert it into a larger one. This is better because the handling code gets simpler and also makes a better room for the upcoming vbroadcast! llvm-svn: 137807
* Add support for ext and ins.Akira Hatanaka2011-08-174-1/+170
| | | | llvm-svn: 137804
* Unbork Windows build. Thanks, Francois.Jordy Rose2011-08-171-2/+2
| | | | llvm-svn: 137798
* Use DynamicLibrary instances as a way to get symbols from a specific ↵Jordy Rose2011-08-172-67/+109
| | | | | | library. Preparation for upcoming (preliminary) support for plugins for the static analyzer. llvm-svn: 137791
* Thumb ADD(immediate) parsing support.Jim Grosbach2011-08-162-3/+8
| | | | llvm-svn: 137788
* Separate out Thumb1 instructions that need an S bit operand from those that ↵Owen Anderson2011-08-162-0/+9
| | | | | | do not, for the purposes of decoding them. llvm-svn: 137787
* Extend the undef ^ undef idiom once more. No testcase: I can't figure out ↵Eli Friedman2011-08-161-4/+5
| | | | | | how to actually trigger the codepath in question at the moment, but it might get exposed in the future. llvm-svn: 137781
* Thumb parsing diagnostics for low-reg requirements on ADD and MOV.Jim Grosbach2011-08-163-15/+38
| | | | llvm-svn: 137779
* Until now all debug info MDNodes referred to a root MDNode, a compile unit. ↵Devang Patel2011-08-166-170/+218
| | | | | | | | This simplified handling of these needs in dwarf writer. However, one side effect of this is that during link time optimization all these MDNodes are _not_ uniqued. In other words there will be N number of MDNodes describing "int", "char" and all other types, which would suddenly grow when each object file starts using libraries like STL. MDNodes graph structure such that compiler unit keeps track of important MDNodes and update dwarf writer to process mdnodes top-down instead of bottom up. llvm-svn: 137778
* A bunch of misc fixes to SCCPSolver::ResolvedUndefsIn, including a fix to stopEli Friedman2011-08-161-40/+72
| | | | | | | | | making random bad assumptions about instructions which are not explicitly listed. Includes fix for rdar://9956541, a version of "undef ^ undef should return 0 because it's easier than arguing with users". llvm-svn: 137777
* Add missing exit for 'case'.Jim Grosbach2011-08-161-0/+1
| | | | llvm-svn: 137774
* Thumb assembly parsing and encoding for ADD(register) instruction.Jim Grosbach2011-08-161-0/+9
| | | | llvm-svn: 137759
* The resume instruction may throw. Return 'true' in this case.Bill Wendling2011-08-161-1/+1
| | | | llvm-svn: 137757
* Move some logic into a helper function and expand the commentary.Jim Grosbach2011-08-161-13/+28
| | | | llvm-svn: 137756
* Minor bug in SCCP found by inspection. (I don't think it's possible to hit ↵Eli Friedman2011-08-161-0/+7
| | | | | | this with a normal pass pipeline, but fixing for completeness.) llvm-svn: 137755
* ARM thumb assembly parsing for arithmetic flag setting instructions.Jim Grosbach2011-08-163-1/+62
| | | | | | | | | Thumb one requires that many arithmetic instruction forms have an 'S' suffix. For Thumb2, the whether the suffix is required or precluded depends on whether the instruction is in an IT block. Use target parser predicates to check for these sorts of context-sensitive constraints. llvm-svn: 137746
* Use the getFirstInsertionPt() method instead of getFirstNonPHI + an 'isa<>'Bill Wendling2011-08-165-24/+12
| | | | | | check for a LandingPadInst. llvm-svn: 137745
* Add getFirstInsertionPt() method.Bill Wendling2011-08-161-0/+6
| | | | | | | | getFirstInsertionPt() returns an iterator to the first insertion point in a basic block. This is after all PHIs and any other instruction which is required to be at the top of the basic block (like LandingPadInst). llvm-svn: 137744
* I think there was some confusion about what I meant. :-) Replacing the comment.Bill Wendling2011-08-161-1/+4
| | | | llvm-svn: 137743
* Remove unused Target argument from AsmParser construction methods.Jim Grosbach2011-08-163-6/+6
| | | | | | The argument is unused, and is a layering violation in any case. llvm-svn: 137735
* Instead of always leaving the work to the generic legalizer whenBruno Cardoso Lopes2011-08-161-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | there is no support for native 256-bit shuffles, be more smart in some cases, for example, when you can extract specific 128-bit parts and use regular 128-bit shuffles for them. Example: For this shuffle: shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 0, i32 7, i32 6> This was expanded to: vextractf128 $1, %ymm1, %xmm2 vpextrq $0, %xmm2, %rax vmovd %rax, %xmm1 vpextrq $1, %xmm2, %rax vmovd %rax, %xmm2 vpunpcklqdq %xmm1, %xmm2, %xmm1 vpextrq $0, %xmm0, %rax vmovd %rax, %xmm2 vpextrq $1, %xmm0, %rax vmovd %rax, %xmm0 vpunpcklqdq %xmm2, %xmm0, %xmm0 vinsertf128 $1, %xmm1, %ymm0, %ymm0 ret Now we get: vshufpd $1, %xmm0, %xmm0, %xmm0 vextractf128 $1, %ymm1, %xmm1 vshufpd $1, %xmm1, %xmm1, %xmm1 vinsertf128 $1, %xmm1, %ymm0, %ymm0 llvm-svn: 137733
* Remove unnecessary version check.Devang Patel2011-08-161-2/+1
| | | | llvm-svn: 137728
* ARM .align NOP padding uses different encoding pre-ARMv6.Jim Grosbach2011-08-161-14/+37
| | | | | | Patch by Kristof Beyls and James Malloy. llvm-svn: 137723
* Revert r137562 because it caused PR10674Nadav Rotem2011-08-161-7/+0
| | | | llvm-svn: 137719
* Add a mechanism for optimisation plugins to register passes that all front ↵David Chisnall2011-08-161-0/+15
| | | | | | | | ends can use without needing to be aware of the plugin (or the plugin be aware of the front end). Before 3.0, I'd like to add a mechanism for automatically loading a set of plugins from a config file. API suggestions welcome... llvm-svn: 137717
* A few places where we want to skip the landingpad instruction for insertion.Bill Wendling2011-08-163-2/+8
| | | | llvm-svn: 137712
* Fix handling of double precision loads and stores when Mips1 is targeted. Akira Hatanaka2011-08-166-167/+73
| | | | | | | | | | | | | | | Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. llvm-svn: 137711
* Define function MipsMCInstLower::LowerOperand. Akira Hatanaka2011-08-162-25/+29
| | | | llvm-svn: 137707
* Add parameter Offset to MipsMCInstLower::LowerSymbolOperand. Akira Hatanaka2011-08-162-5/+5
| | | | llvm-svn: 137706
* Revert a bit of r137667; the logic in question can safely handle atomic ↵Eli Friedman2011-08-161-4/+4
| | | | | | load/store. llvm-svn: 137702
* After talking with Bill, it seems like the LandingPad handling here is likelyEli Friedman2011-08-161-4/+1
| | | | | | to be wrong (or at least somewhat suspect). Leave a FIXME for Bill. llvm-svn: 137694
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