diff options
author | Jim Grosbach <grosbach@apple.com> | 2011-08-17 19:55:51 +0000 |
---|---|---|
committer | Jim Grosbach <grosbach@apple.com> | 2011-08-17 19:55:51 +0000 |
commit | 3b5a69cc45a99ad86b8dc4ccc016ba9cf9e5e3f2 (patch) | |
tree | ad7a751202a8ec7ce131db941be2bf9dd9b15ef9 /llvm/lib | |
parent | 863752388662182e59f1647c4275359950ee182a (diff) | |
download | bcm5719-llvm-3b5a69cc45a99ad86b8dc4ccc016ba9cf9e5e3f2.tar.gz bcm5719-llvm-3b5a69cc45a99ad86b8dc4ccc016ba9cf9e5e3f2.zip |
80 columns.
llvm-svn: 137857
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp index 53476def9d4..dd066e891c3 100644 --- a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -240,7 +240,8 @@ void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB, Bytes -= ThisVal; const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); const MachineInstrBuilder MIB = - AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg).setMIFlags(MIFlags)); + AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg) + .setMIFlags(MIFlags)); AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); } else { AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) |