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author | Jim Grosbach <grosbach@apple.com> | 2011-08-16 23:57:34 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2011-08-16 23:57:34 +0000 |
commit | e9ab47a72a7bead93c691a820cb803d20756a7b6 (patch) | |
tree | ad091f35eca87436224a4db8c59a74084eea6e1a /llvm/lib | |
parent | 91a8f9be203b7aac0fe58d6c0f577f62d70c03df (diff) | |
download | bcm5719-llvm-e9ab47a72a7bead93c691a820cb803d20756a7b6.tar.gz bcm5719-llvm-e9ab47a72a7bead93c691a820cb803d20756a7b6.zip |
Thumb ADD(immediate) parsing support.
llvm-svn: 137788
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 6 | ||||
-rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 5 |
2 files changed, 8 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index 85ffe928a9d..ffc74990dd2 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -849,7 +849,7 @@ def tADC : // A8.6.2 // Add immediate def tADDi3 : // A8.6.4 T1 - T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), + T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), IIC_iALUi, "add", "\t$Rd, $Rm, $imm3", [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> { @@ -858,8 +858,8 @@ def tADDi3 : // A8.6.4 T1 } def tADDi8 : // A8.6.4 T2 - T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), - IIC_iALUi, + T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), + (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, "add", "\t$Rdn, $imm8", [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>; diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 3db8a7d4d1e..0313ef4b71e 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -3013,6 +3013,11 @@ processInstruction(MCInst &Inst, Inst = TmpInst; } break; + case ARM::tADDi8: + // If the immediate is in the range 0-7, we really wanted tADDi3. + if (Inst.getOperand(3).getImm() < 8) + Inst.setOpcode(ARM::tADDi3); + break; } } |