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* [SLP] limit vectorization of Constant subclasses (PR33958)Sanjay Patel2019-09-151-2/+5
| | | | | | | | | | | | | | This is a fix for: https://bugs.llvm.org/show_bug.cgi?id=33958 It seems universally true that we would not want to transform this kind of sequence on any target, but if that's not correct, then we could view this as a target-specific cost model problem. We could also white-list ConstantInt, ConstantFP, etc. rather than blacklist Global and ConstantExpr. Differential Revision: https://reviews.llvm.org/D67362 llvm-svn: 371931
* [TargetLowering] SimplifyDemandedBits - add EXTRACT_SUBVECTOR support.Simon Pilgrim2019-09-141-0/+15
| | | | | | Call SimplifyDemandedBits on the source vector. llvm-svn: 371923
* [InstSimplify] simplifyUnsignedRangeCheck(): handle few tautological cases ↵Roman Lebedev2019-09-141-16/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | (PR43251) Summary: This is split off from D67356, since these cases produce a constant, no real need to keep them in instcombine. Alive proofs: https://rise4fun.com/Alive/u7Fk https://rise4fun.com/Alive/4lV https://bugs.llvm.org/show_bug.cgi?id=43251 Reviewers: spatel, nikic, xbolva00 Reviewed By: spatel Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67498 llvm-svn: 371921
* [ScheduleDAGMILive] Fix typo in comment.Mingjie Xing2019-09-141-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D67478 llvm-svn: 371916
* [Attributor][Fix] Use right type to replace expressionsJohannes Doerfert2019-09-141-3/+8
| | | | | | | | | | | | | | Summary: This should be obsolete once the functionality in D66967 is integrated. Reviewers: uenoku, sstefan1 Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67231 llvm-svn: 371915
* [Reproducer] Add reproducer dump command.Jonas Devlieghere2019-09-131-10/+12
| | | | | | | | | | | This adds a reproducer dump commands which makes it possible to inspect a reproducer from inside LLDB. Currently it supports the Files, Commands and Version providers. I'm planning to add support for the GDB Remote provider in a follow-up patch. Differential revision: https://reviews.llvm.org/D67474 llvm-svn: 371909
* [WebAssembly] Narrowing and widening SIMD opsThomas Lively2019-09-131-0/+36
| | | | | | | | | | | | | | | | Summary: Implements target-specific LLVM intrinsics and clang builtins for these new SIMD operations, as described at https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#integer-to-integer-narrowing. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D67425 llvm-svn: 371906
* [GlobalISel] Fix insertion point of new instructions to be after PHIs.Amara Emerson2019-09-131-3/+3
| | | | | | | | | | For some reason we sometimes insert new instructions one instruction before the first non-PHI when legalizing. This can result in having non-PHI instructions before PHIs, which mean that PHI elimination doesn't catch them. Differential Revision: https://reviews.llvm.org/D67570 llvm-svn: 371901
* Add dependency from Orc to PassesSanjoy Das2019-09-131-2/+2
| | | | | | | | | | | | | | Summary: Orc uses registerFunctionAnalyses that's defined in Passes. Reviewers: dblaikie Subscribers: mcrosier, bixia, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67477 llvm-svn: 371898
* [AArch64][GlobalISel] Tail call memory intrinsicsJessica Paquette2019-09-132-1/+46
| | | | | | | | | | | | | | | | | | | | | | Because memory intrinsics are handled differently than other calls, we need to check them for tail call eligiblity in the legalizer. This allows us to still inline them when it's beneficial to do so, but also tail call when possible. This adds simple tail calling support for when the intrinsic is followed by a return. It ports the attribute checks from `TargetLowering::isInTailCallPosition` into a similarly-named function in LegalizerHelper.cpp. The target-specific `isUsedByReturnOnly` hook is not ported here. Update tailcall-mem-intrinsics.ll to show that GlobalISel can now tail call memory intrinsics. Update legalize-memcpy-et-al.mir to have a case where we don't tail call. Differential Revision: https://reviews.llvm.org/D67566 llvm-svn: 371893
* [Support] Add overload writeFileAtomically(std::function Writer)Jan Korous2019-09-132-30/+65
| | | | | | Differential Revision: https://reviews.llvm.org/D67424 llvm-svn: 371890
* [aarch64] move custom isel of extract_vector_elt to td file - NFCSebastian Pop2019-09-132-43/+10
| | | | | | | | | | | | | | | | | | | In preparation for def-pat selection of dot product instructions, this patch moves the custom instruction selection of extract_vector_elt to the td file. Without this change it is impossible to catch a pattern that starts with an extract_vector_elt: the custom cpp code is executed first ahead of the patterns in the td files that are only executed at the end of the switch statement in SelectCode(Node). With this patch applied, it becomes possible to select a different pattern that starts with extract_vector_elt by selecting a higher complexity than this pattern. The patch has been tested on aarch64-linux with make check-all. Differential Revision: https://reviews.llvm.org/D67497 llvm-svn: 371887
* AArch64: fix EXPENSIVE_CHECKS for arm64_32.Tim Northover2019-09-131-1/+1
| | | | | | | For some reason I'd decided to mark the end-result of a GOT load as dead. It's clearly not (necessarily). llvm-svn: 371883
* Revert for: [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.Alexander Timofeev2019-09-134-64/+19
| | | | llvm-svn: 371873
* [AArch64][GlobalISel] Add support for sibcalling callees with varargsJessica Paquette2019-09-131-6/+19
| | | | | | | | | | | | | | | This adds support for tail calling callees with varargs, equivalent to how it is done in AArch64ISelLowering. This only works for sibling calls, and does not add the necessary support for musttail with varargs. (See r345641 for equivalent ISelLowering support.) This should be implemented when we stop falling back on musttail. Update call-translator-tail-call.ll to show that we can now tail call varargs. Differential Revision: https://reviews.llvm.org/D67518 llvm-svn: 371868
* [yaml2obj/ObjectYAML] - Cleanup the error reporting API, add custom errors ↵George Rimar2019-09-136-298/+258
| | | | | | | | | | | | | | | | | | | | | handlers. This is a continuation of the YAML library error reporting refactoring/improvement and the idea by itself was mentioned in the following thread: https://reviews.llvm.org/D67182?id=218714#inline-603404 This performs a cleanup of all object emitters in the library. It allows using the custom one provided by the caller. One of the nice things is that each tool can now print its tool name, e.g: "yaml2obj: error: <text>" Also, the code became a bit simpler. Differential revision: https://reviews.llvm.org/D67445 llvm-svn: 371865
* [X86] Use incDecVectorConstant to simplify the min/max code in LowerVSETCC.Craig Topper2019-09-131-14/+12
| | | | | | | incDecVectorConstant is used for a similar reason in LowerVSETCCWithSUBUS so we might as well share the code. llvm-svn: 371861
* [Orc] Roll back ThreadPool to std::functionBenjamin Kramer2019-09-131-1/+3
| | | | | | MSVC doesn't allow move-only types in std::packaged_task. Boo. llvm-svn: 371844
* [Orc] Address the remaining move-capture FIXMEsBenjamin Kramer2019-09-135-24/+18
| | | | | | | This required spreading unique_function a bit more, which I think is a good thing. llvm-svn: 371843
* [X86] negateFMAOpcode - extend to support FMADDSUB/FMSUBADD and output ↵Simon Pilgrim2019-09-131-27/+40
| | | | | | | | | | negation. NFCI. Some prep work for PR42863, this change allows us to move all the FMA opcode mappings into the negateFMAOpcode helper. For the FMADDSUB/FMSUBADD cases, we can only negate the accumulator - any other negations will result in an error. llvm-svn: 371840
* [ARM] Add earlyclobber for cross beat MVE instructionsDavid Green2019-09-131-40/+39
| | | | | | | | | | | | | | | | | | | | | | | | | rL367544 added @earlyclobbers for the MVE VREV64 instruction. This adds the same for a number of other 32bit instructions that are similarly unpredictable if the destination equals the source (due to the cross beat nature of the instructions). This includes: VCADD.f32 VCADD.i32 VCMUL.f32 VHCADD.s32 VMULLT/B.s/u32 VQDMLADH{X}.s32 VQRDMLADH{X}.s32 VQDMLSDH{X}.s32 VQRDMLSDH{X}.s32 VQDMULLT/B.s32 with Qm and Rm No tests here as this would require intrinsics (or very interesting codegen) to manifest. The tests will follow naturally as the intrinsics are added. Differential Revision: https://reviews.llvm.org/D67462 llvm-svn: 371838
* [Alignment] Introduce llvm::Align to MCSectionGuillaume Chatelet2019-09-138-20/+23
| | | | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet, JDevlieghere Subscribers: arsenm, sdardis, jvesely, nhaehnle, sbc100, hiraditya, aheejin, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67486 llvm-svn: 371831
* [lib/ObjectYAML] - Change interface to return `bool` instead of `int`. NFCIGeorge Rimar2019-09-136-31/+29
| | | | | | | | It was suggested in comments for D67445 to split this part. Differential revision: https://reviews.llvm.org/D67488 llvm-svn: 371828
* [ARM] Add support for MVE vmaxv and vminvSam Tebbs2019-09-133-2/+35
| | | | | | | | This patch adds vecreduce_smax, vecredude_umax, vecreduce_smin, vecreduce_umin and selection for vmaxv and minv. Differential Revision: https://reviews.llvm.org/D66413 llvm-svn: 371827
* [BasicBlockUtils] Add optional BBName argument, in line with BB:splitBasicBlockFlorian Hahn2019-09-132-4/+6
| | | | | | | | | | Reviewers: spatel, asbirlea, craig.topper Reviewed By: asbirlea Differential Revision: https://reviews.llvm.org/D67521 llvm-svn: 371819
* [AArch64] MachineCombiner FMA matching. NFC.Sjoerd Meijer2019-09-131-325/+112
| | | | | | | | | Follow-up of rL371321 that added some more FP16 FMA patterns, and an attempt to reduce the copy-pasting and make this more readable. Differential Revision: https://reviews.llvm.org/D67403 llvm-svn: 371818
* [TargetRegisterInfo] Remove SVT argument from getCommonSubClass.Craig Topper2019-09-132-14/+6
| | | | | | | | This was added to support fp128 on x86-64, but appears to be unneeded now. This may be because the FR128 register class added back then was merged with the VR128 register class later. llvm-svn: 371815
* AMDGPU/GlobalISel: Fix assert on multi-return side effect intrinsicsMatt Arsenault2019-09-131-1/+1
| | | | | | llvm.amdgcn.else hits this. llvm-svn: 371812
* AMDGPU/GlobalISel: Legalize s32->s16 G_SITOFP/G_UITOFPMatt Arsenault2019-09-131-1/+1
| | | | llvm-svn: 371811
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-134-27/+45
| | | | | | Differential Revision: https://reviews.llvm.org/D61884 llvm-svn: 371810
* Revert "[RISCV] Support stack offset exceed 32-bit for RV64"Shiva Chen2019-09-134-44/+27
| | | | | | This reverts commit 1c340c62058d4115d21e5fa1ce3a0d094d28c792. llvm-svn: 371809
* AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.elseMatt Arsenault2019-09-131-0/+7
| | | | llvm-svn: 371808
* AMDGPU/GlobalISel: Select 16-bit VALU bit opsMatt Arsenault2019-09-131-3/+3
| | | | llvm-svn: 371807
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-134-27/+44
| | | | | | Differential Revision: https://reviews.llvm.org/D61884 llvm-svn: 371806
* AMDGPU/GlobalISel: Legalize G_FFLOORMatt Arsenault2019-09-132-2/+3
| | | | llvm-svn: 371803
* Temporarily revert r371640 "LiveIntervals: Split live intervals on multiple ↵Tim Shen2019-09-131-11/+1
| | | | | | | | dead defs". It reveals a miscompile on Hexagon. See PR43302 for details. llvm-svn: 371802
* AMDGPU/GlobalISel: Legalize G_FMADMatt Arsenault2019-09-134-0/+51
| | | | | | | | | | | | | | | Unlike SelectionDAG, treat this as a normally legalizable operation. In SelectionDAG this is supposed to only ever formed if it's legal, but I've found that to be restricting. For AMDGPU this is contextually legal depending on whether denormal flushing is allowed in the use function. Technically we currently treat the denormal mode as a subtarget feature, so custom lowering could be avoided. However I consider this to be a defect, and this should be contextually dependent on the controllable rounding mode of the parent function. llvm-svn: 371800
* AMDGPU/GlobalISel: Select G_CTPOPMatt Arsenault2019-09-134-2/+15
| | | | llvm-svn: 371798
* DAG/GlobalISel: Correct type profile of bitcount opsMatt Arsenault2019-09-137-21/+21
| | | | | | | | The result integer does not need to be the same width as the input. AMDGPU, NVPTX, and Hexagon all have patterns working around the types matching. GlobalISel defines these as being different type indexes. llvm-svn: 371797
* LiveIntervals: Remove assertionMatt Arsenault2019-09-121-1/+2
| | | | | | | | | | | | | This testcase is invalid, and caught by the verifier. For the verifier to catch it, the live interval computation needs to complete. Remove the assert so the verifier catches this, which is less confusing. In this testcase there is an undefined use of a subregister, and lanes which aren't used or defined. An equivalent testcase with the super-register shrunk to have no untouched lanes already hit this verifier error. llvm-svn: 371792
* AMDGPU: Inline constant when materalizing FI with add on gfx9Matt Arsenault2019-09-122-3/+6
| | | | | | | | | This was relying on the SGPR usable for the carry out clobber to also be used for the input. There was no carry out on gfx9. With no carry out clobber to worry about, so the literal can just be directly used with a VOP2 add. llvm-svn: 371791
* Rename nonvolatile_load/store to simple_load/store [NFC]Philip Reames2019-09-126-31/+31
| | | | | | Implement the TODO from D66318. llvm-svn: 371789
* [AArch64][GlobalISel] Support tail calling with swiftself parametersJessica Paquette2019-09-121-5/+32
| | | | | | | | | | | | | | | | Swiftself uses a callee-saved register. We can tail call when the register used in the caller and callee is the same. This behaviour is equivalent to that in `TargetLowering::parametersInCSRMatch`. Update call-translator-tail-call.ll to verify that we can do this. When we support inline assembly, we can write a check similar to the one in the general swiftself.ll. For now, we need to verify that we get the correct COPY instruction after call lowering. Differential Revision: https://reviews.llvm.org/D67511 llvm-svn: 371788
* [SDAG] Update generic code to conservatively check for isAtomic in addition ↵Philip Reames2019-09-124-49/+80
| | | | | | | | | | to isVolatile This is the first sweep of generic code to add isAtomic bailouts where appropriate. The intention here is to have the switch from AtomicSDNode to LoadSDNode/StoreSDNode be close to NFC; that is, I'm not looking to allow additional optimizations at this time. That will come later. See D66309 for context. Differential Revision: https://reviews.llvm.org/D66318 llvm-svn: 371786
* [AArch64][GlobalISel] Support sibling calls with outgoing argumentsJessica Paquette2019-09-123-25/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for lowering sibling calls with outgoing arguments. e.g ``` define void @foo(i32 %a) ``` Support is ported from AArch64ISelLowering's `isEligibleForTailCallOptimization`. The only thing that is missing is a full port of `TargetLowering::parametersInCSRMatch`. So, if we're using swiftself, we'll never tail call. - Rename `analyzeCallResult` to `analyzeArgInfo`, since the function is now used for both outgoing and incoming arguments - Teach `OutgoingArgHandler` about tail calls. Tail calls use frame indices for stack arguments. - Teach `lowerFormalArguments` to set the bytes in the caller's stack argument area. This is used later to check if the tail call's parameters will fit on the caller's stack. - Add `areCalleeOutgoingArgsTailCallable` to perform the eligibility check on the callee's outgoing arguments. For testing: - Update call-translator-tail-call to verify that we can now tail call with outgoing arguments, use G_FRAME_INDEX for stack arguments, and respect the size of the caller's stack - Remove GISel-specific check lines from speculation-hardening.ll, since GISel now tail calls like the other selectors - Add a GISel test line to tailcall-string-rvo.ll since we can tail call in that test now - Add a GISel test line to tailcall_misched_graph.ll since we tail call there now. Add specific check lines for GISel, since the debug output from the machine-scheduler differs with GlobalISel. The dependency still holds, but the output comes out in a different order. Differential Revision: https://reviews.llvm.org/D67471 llvm-svn: 371780
* [PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC ↵Craig Topper2019-09-128-47/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register class. Summary: Since the SPE4RC register class contains an identical set of registers and an identical spill size to the GPRC class its slightly confusing the tablegen emitter. It's preventing the GPRC_and_GPRC_NOR0 synthesized register class from inheriting VTs and AltOrders from GPRC or GPRC_NOR0. This is because SPE4C is found first in the super register class list when inheriting these properties and it doesn't set the VTs or AltOrders the same way as GPRC or GPRC_NOR0. This patch replaces all uses of GPE4RC with GPRC and allows GPRC and GPRC_NOR0 to contain f32. The test changes here are because the AltOrders are being inherited to GPRC_NOR0 now. Found while trying to determine if getCommonSubClass needs to take a VT argument. It was originally added to support fp128 on x86-64, I've changed some things about that so that it might be needed anymore. But a PowerPC test crashed without it and I think its due to this subclass issue. Reviewers: jhibbits, nemanjai, kbarton, hfinkel Subscribers: wuzish, nemanjai, mehdi_amini, hiraditya, kbarton, MaskRay, dexonsmith, jsji, shchenz, steven.zhang, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67513 llvm-svn: 371779
* [SCEV] Add smin support to getRangeRefPhilip Reames2019-09-121-0/+8
| | | | | | | | We were failing to compute trip counts (both exact and maximum) for any loop which involved a comparison against either an umin or smin. It looks like this simply got missed when we added smin/umin to SCEV. (Note: umin was submitted separately earlier today. Turned out two folks hit this at the same time.) Differential Revision: https://reviews.llvm.org/D67514 llvm-svn: 371776
* [DAGCombiner][X86] Pass the CmpOpVT to reduceSelectOfFPConstantLoads so X86 ↵Craig Topper2019-09-123-3/+4
| | | | | | | | | | | can exclude fp128 compares. The X86 decision assumes the compare will produce a result in an XMM register, but that can't happen for an fp128 compare since those go to a libcall the returns an i32. Pass the VT so X86 can check the type. llvm-svn: 371775
* [ConstantFolding] Expand folding of some library functionsEvandro Menezes2019-09-121-3/+22
| | | | | | | | | Expanding the folding of `nearbyint()`, `rint()` and `trunc()` to library functions, in addition to the current support for intrinsics. Differential revision: https://reviews.llvm.org/D67468 llvm-svn: 371774
* [SelectionDAGBuilder] Simplify loop in visitSelect back to how it was before ↵Craig Topper2019-09-121-2/+1
| | | | | | | | | | | | | r255558. This code was changed to accomodate fp128 being softened to itself during type legalization on x86-64. This was done in order to create libcalls while having fp128 as a legal type. We're now doing the libcall creation during LegalizeDAG and the type legalization changes to enable the old behavior have been removed. So this change to SelectionDAGBuilder is no longer needed. llvm-svn: 371771
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