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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-13 03:55:49 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-13 03:55:49 +0000 |
| commit | 67d9349dad3f4a950e6a389748feb028abb00537 (patch) | |
| tree | e96137a2445f4d088ee0c56fe026b71d3553d7ef /llvm/lib | |
| parent | 638f802381178350c0897659515607b92bd20dcb (diff) | |
| download | bcm5719-llvm-67d9349dad3f4a950e6a389748feb028abb00537.tar.gz bcm5719-llvm-67d9349dad3f4a950e6a389748feb028abb00537.zip | |
AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.else
llvm-svn: 371808
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index d5057f300fa..50977afba5f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -2285,6 +2285,13 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); break; } + case Intrinsic::amdgcn_else: { + unsigned WaveSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI); + OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); + OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize); + OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize); + break; + } } break; } |
