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* [x86] Remove the insanely over-aggressive unpack lowering strategy forChandler Carruth2015-02-191-38/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | v16i8 shuffles, and replace it with new facilities. This uses precise patterns to match exact unpacks, and the new generalized unpack lowering only when we detect a case where we will have to shuffle both inputs anyways and they terminate in exactly a blend. This fixes all of the blend horrors that I uncovered by always lowering blends through the vector shuffle lowering. It also removes *sooooo* much of the crazy instruction sequences required for v16i8 lowering previously. Much cleaner now. The only "meh" aspect is that we sometimes use pshufb+pshufb+unpck when it would be marginally nicer to use pshufb+pshufb+por. However, the difference there is *tiny*. In many cases its a win because we re-use the pshufb mask. In others, we get to avoid the pshufb entirely. I've left a FIXME, but I'm dubious we can really do better than this. I'm actually pretty happy with this lowering now. For SSE2 this exposes some horrors that were really already there. Those will have to fixed by changing a different path through the v16i8 lowering. llvm-svn: 229846
* [mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generatorJozef Kolek2015-02-191-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D7611 llvm-svn: 229845
* [x86] The SELECT x86 DAG combine also does legalization. It used to relyChandler Carruth2015-02-191-6/+6
| | | | | | | | | | | | | | | | | | | on things not being marked as either custom or legal, but we now do custom lowering of more VSELECT nodes. To cope with this, manually replicate the legality tests here. These have to stay in sync with the set of tests used in the custom lowering of VSELECT. Ideally, we wouldn't do any of this combine-based-legalization when we have an actual custom legalization step for VSELECT, but I'm not going to be able to rewrite all of that today. I don't have a test case for this currently, but it was found when compiling a number of the test-suite benchmarks. I'll try to reduce a test case and add it. This should at least fix the test-suite fallout on build bots. llvm-svn: 229844
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-1925-267/+244
| | | | llvm-svn: 229841
* Implement invoke statepoint verification.Igor Laevsky2015-02-191-9/+49
| | | | | | Differential Revision: http://reviews.llvm.org/D7366 llvm-svn: 229840
* Add invoke related functionality into StatepointSite classes.Igor Laevsky2015-02-191-4/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D7364 llvm-svn: 229838
* AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics.Elena Demikhovsky2015-02-195-48/+85
| | | | llvm-svn: 229837
* [x86] Add support for bit-wise blending and use it in the v8 and v16Chandler Carruth2015-02-191-1/+39
| | | | | | | | | | | | | | | | | | | | | | | lowering paths. I'm going to be leveraging this to simplify a lot of the overly complex lowering of v8 and v16 shuffles in pre-SSSE3 modes. Sadly, this isn't profitable on v4i32 and v2i64. There, the float and double blending instructions for pre-SSE4.1 are actually pretty good, and we can't beat them with bit math. And once SSE4.1 comes around we have direct blending support and this ceases to be relevant. Also, some of the test cases look odd because the domain fixer canonicalizes these to floating point domain. That's OK, it'll use the integer domain when it matters and some day I may be able to update enough of LLVM to canonicalize the other way. This restores almost all of the regressions from teaching x86's vselect lowering to always use vector shuffle lowering for blends. The remaining problems are because the v16 lowering path is still doing crazy things. I'll be re-arranging that strategy in more detail in subsequent commits to finish recovering the performance here. llvm-svn: 229836
* [x86,sdag] Two interrelated changes to the x86 and sdag code.Chandler Carruth2015-02-192-50/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, don't combine bit masking into vector shuffles (even ones the target can handle) once operation legalization has taken place. Custom legalization of vector shuffles may exist for these patterns (making the predicate return true) but that custom legalization may in some cases produce the exact bit math this matches. We only really want to handle this prior to operation legalization. However, the x86 backend, in a fit of awesome, relied on this. What it would do is mark VSELECTs as expand, which would turn them into arithmetic, which this would then match back into vector shuffles, which we would then lower properly. Amazing. Instead, the second change is to teach the x86 backend to directly form vector shuffles from VSELECT nodes with constant conditions, and to mark all of the vector types we support lowering blends as shuffles as custom VSELECT lowering. We still mark the forms which actually support variable blends as *legal* so that the custom lowering is bypassed, and the legal lowering can even be used by the vector shuffle legalization (yes, i know, this is confusing. but that's how the patterns are written). This makes the VSELECT lowering much more sensible, and in fact should fix a bunch of bugs with it. However, as you'll see in the test cases, right now what it does is point out the *hilarious* deficiency of the new vector shuffle lowering when it comes to blends. Fortunately, my very next patch fixes that. I can't submit it yet, because that patch, somewhat obviously, forms the exact and/or pattern that the DAG combine is matching here! Without this patch, teaching the vector shuffle lowering to produce the right code infloops in the DAG combiner. With this patch alone, we produce terrible code but at least lower through the right paths. With both patches, all the regressions here should be fixed, and a bunch of the improvements (like using 2 shufps with no memory loads instead of 2 andps with memory loads and an orps) will stay. Win! There is one other change worth noting here. We had hilariously wrong vectorization cost estimates for vselect because we fell through to the code path that assumed all "expand" vector operations are scalarized. However, the "expand" lowering of VSELECT is vector bit math, most definitely not scalarized. So now we go back to the correct if horribly naive cost of "1" for "not scalarized". If anyone wants to add actual modeling of shuffle costs, that would be cool, but this seems an improvement on its own. Note the removal of 16 and 32 "costs" for doing a blend. Even in SSE2 we can blend in fewer than 16 instructions. ;] Of course, we don't right now because of OMG bad code, but I'm going to fix that. Next patch. I promise. llvm-svn: 229835
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-1925-244/+267
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* [Support/Timer] Make GetMallocUsage() aware of jemalloc.Davide Italiano2015-02-191-0/+10
| | | | | | | Differential Revision: D7657 Reviewed by: shankarke, majnemer llvm-svn: 229824
* Provide the same ABI regardless of NDEBUGDmitri Gribenko2015-02-192-30/+38
| | | | | | | | | | | | | | | | | | | | | For projects depending on LLVM, I find it very useful to combine a release-no-asserts build of LLVM with a debug+asserts build of the dependent project. The motivation is that when developing a dependent project, you are debugging that project itself, not LLVM. In my usecase, a significant part of the runtime is spent in LLVM optimization passes, so I would like to build LLVM without assertions to get the best performance from this combination. Currently, `lib/Support/Debug.cpp` changes the set of symbols it provides depending on NDEBUG, while `include/llvm/Support/Debug.h` requires extra symbols when NDEBUG is not defined. Thus, it is not possible to enable assertions in an external project that uses facilities of `Debug.h`. This patch changes `Debug.cpp` and `Valgrind.cpp` to always define the symbols that other code may depend on when #including LLVM headers without NDEBUG. http://reviews.llvm.org/D7662 llvm-svn: 229819
* Remove the local subtarget variable from the SystemZ asm printerEric Christopher2015-02-192-8/+3
| | | | | | and update the two calls accordingly. llvm-svn: 229805
* Remove a few more calls to TargetMachine::getSubtarget from theEric Christopher2015-02-192-4/+4
| | | | | | R600 port. llvm-svn: 229804
* Grab the subtarget off of the machine function for the R600Eric Christopher2015-02-192-15/+14
| | | | | | asm printer and clean up a bunch of uses. llvm-svn: 229803
* Remove the DisasmEnabled AsmPrinter variable and just look itEric Christopher2015-02-193-6/+3
| | | | | | | up on the subtarget where it's set anyhow than looking it up 2-3 times in the same place. llvm-svn: 229802
* MC: Remove NullStreamer hook, as it is redundant with NullTargetStreamer.Peter Collingbourne2015-02-194-23/+10
| | | | llvm-svn: 229799
* Introduce Target::createNullTargetStreamer and use it from IRObjectFile.Peter Collingbourne2015-02-194-0/+18
| | | | | | | | | A null MCTargetStreamer allows IRObjectFile to ignore target-specific directives. Previously we were crashing. Differential Revision: http://reviews.llvm.org/D7711 llvm-svn: 229797
* [objc-arc] Introduce the concept of RCIdentity and rename all relevant ↵Michael Gottesman2015-02-195-53/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | functions to use that name. NFC. The RCIdentity root ("Reference Count Identity Root") of a value V is a dominating value U for which retaining or releasing U is equivalent to retaining or releasing V. In other words, ARC operations on V are equivalent to ARC operations on U. This is a useful property to ascertain since we can use this in the ARC optimizer to make it easier to match up ARC operations by always mapping ARC operations to RCIdentityRoots instead of pointers themselves. Then we perform pairing of retains, releases which are applied to the same RCIdentityRoot. In general, the two ways that we see RCIdentical values in ObjC are via: 1. PointerCasts 2. Forwarding Calls that return their argument verbatim. As such in ObjC, two RCIdentical pointers must always point to the same memory location. Previously this concept was implicit in the code and various methods that dealt with this concept were given functional names that did not conform to any name in the "ARC" model. This often times resulted in code that was hard for the non-ARC acquanted to understand resulting in unhappiness and confusion. llvm-svn: 229796
* [objc-arc-contract] Rename contractRelease => ↵Michael Gottesman2015-02-191-4/+8
| | | | | | | | tryToContractReleaseIntoStoreStrong. NFC. Makes it clearer what this method is actually supposed to do. llvm-svn: 229795
* [objc-arc-contract] Refactor out tryToPeepholeInstruction into its own ↵Michael Gottesman2015-02-191-58/+85
| | | | | | | | | method. NFC. The main method of ObjCARCContract is really large and busy. By refactoring this out, it becomes easier to reason about. llvm-svn: 229794
* [objc-arc-contract] Reorganize the code a bit and make the debug output ↵Michael Gottesman2015-02-191-63/+73
| | | | | | easier to read. llvm-svn: 229793
* IR: Drop scope from MDTemplateParameterDuncan P. N. Exon Smith2015-02-196-56/+37
| | | | | | | | | | Follow-up to r229740, which removed `DITemplate*::getContext()` after my upgrade script revealed that scopes are always `nullptr` for template parameters. This is the other shoe: drop `scope:` from `MDTemplateParameter` and its two subclasses. (Note: a bitcode upgrade would be pointless, since the hierarchy hasn't been moved into place.) llvm-svn: 229791
* Avoid using a self-referential initializer and fix up uses.Eric Christopher2015-02-191-3/+3
| | | | llvm-svn: 229790
* 80-column fixups.Eric Christopher2015-02-191-8/+7
| | | | llvm-svn: 229789
* Remove all use of is64bit off of NVPTXSubtarget and clean up codeEric Christopher2015-02-1912-89/+61
| | | | | | | accordingly. This changes the constructors of a number of classes that don't need to know the subtarget's 64-bitness. llvm-svn: 229787
* Remove all use of getDrvInterface off of NVPTXSubtarget and cleanEric Christopher2015-02-194-51/+23
| | | | | | | up code accordingly. Delete code that was checking for all cases of an enum. llvm-svn: 229786
* Migrate the NVPTX backend asm printer to a per function subtarget.Eric Christopher2015-02-196-58/+74
| | | | | | | | | | | This involved moving two non-subtarget dependent features (64-bitness and the driver interface) to the NVPTX target machine and updating the uses (or migrating around the subtarget use for ease of review). Otherwise use the cached subtarget or create a default subtarget based on the TargetMachine cpu and feature string for the module level assembler emission. llvm-svn: 229785
* IR: Allow MDSubrange to have 'count: -1'Duncan P. N. Exon Smith2015-02-181-1/+1
| | | | | | | | | | | | | | It turns out that `count: -1` is a special value indicating an empty array, such as `Values` in: struct T { unsigned Count; int Values[]; }; Handle it. llvm-svn: 229769
* Add an IR-to-IR test for dwarf EH preparation using optReid Kleckner2015-02-181-0/+8
| | | | | | | This tests the simple resume instruction elimination logic that we have before making some changes to it. llvm-svn: 229768
* Style and formatting fixes for r229715Andrew Kaylor2015-02-181-1/+0
| | | | llvm-svn: 229758
* R600/SI: Fix READLANE and WRITELANE lane select for VIMarek Olsak2015-02-182-6/+6
| | | | | | | | | | | | VOP2 declares vsrc1, but VOP3 declares src1. We can't use the same "ins" if the operands have different names in VOP2 and VOP3 encodings. This fixes a hang in geometry shaders which spill M0 on VI. (BTW it doesn't look like M0 needs spilling and the spilling seems duplicated 3 times) llvm-svn: 229752
* R600/SI: Simplify verification of AMDGPU::OPERAND_REG_INLINE_CMarek Olsak2015-02-181-8/+6
| | | | llvm-svn: 229751
* R600/SI: Remove explicit VOP operand checkingMarek Olsak2015-02-181-28/+0
| | | | | | This should be handled by the OperandType checking. llvm-svn: 229750
* IR: Swap order of name and value in MDEnumDuncan P. N. Exon Smith2015-02-182-3/+3
| | | | | | | | | Put the name before the value in assembly for `MDEnum`. While working on the testcase upgrade script for the new hierarchy, I noticed that it "looks nicer" to have the name first, since it lines the names up in the (somewhat typical) case that they have a common prefix. llvm-svn: 229747
* IR: Add MDSubprogram::replaceFunction()Duncan P. N. Exon Smith2015-02-181-0/+6
| | | | llvm-svn: 229742
* IR: Drop the scope in DI template parametersDuncan P. N. Exon Smith2015-02-182-6/+6
| | | | | | | | | | | The scope/context is always the compile unit, which we replace with `nullptr` anyway (via `getNonCompileUnitScope()`). Drop it explicitly. I noticed this field was always null while writing testcase upgrade scripts to transition to the new hierarchy. Seems wasteful to transition it over if it's already out-of-use. llvm-svn: 229740
* Fix -DNDEBUG -Werror build after r229733Duncan P. N. Exon Smith2015-02-181-0/+2
| | | | llvm-svn: 229736
* dos2unix the WinEH file and testsReid Kleckner2015-02-181-391/+391
| | | | llvm-svn: 229735
* IR: isScopeRef() should check isScope()Duncan P. N. Exon Smith2015-02-181-1/+3
| | | | | | | r229733 removed an invalid use of `DIScopeRef`, so now we can enforce that a `DIScopeRef` is actually a scope. llvm-svn: 229734
* IR: Avoid DIScopeRef in DIImportedEntity::getEntity()Duncan P. N. Exon Smith2015-02-181-0/+17
| | | | | | | | | | `DIImportedEntity::getEntity()` currently returns a `DIScopeRef`, but the nodes it references aren't always `DIScope`s. In particular, it can reference global variables. Introduce `DIDescriptorRef` to avoid the lie. llvm-svn: 229733
* Partial fix for bug 22589Sanjoy Das2015-02-181-23/+39
| | | | | | | | | | | Don't spend the entire iteration space in the scalar loop prologue if computing the trip count overflows. This change also gets rid of the backedge check in the prologue loop and the extra check for overflowing trip-count. Differential Revision: http://reviews.llvm.org/D7715 llvm-svn: 229731
* InstrProf: Don't combine expansion regions with code regionsJustin Bogner2015-02-181-1/+1
| | | | | | | | This was leading to duplicate counts when a code region happened to overlap exactly with an expansion. The combining behaviour only makes sense for code regions. llvm-svn: 229723
* Remove unused member variables (-Wunused-private-field)David Blaikie2015-02-181-7/+3
| | | | llvm-svn: 229722
* InstrProf: Handle unknown functions if they consist only of zero-regionsJustin Bogner2015-02-181-10/+11
| | | | | | | | | | This comes up when we generate coverage for a function but don't end up emitting the function at all - dead static functions or inline functions that aren't referenced in a particular TU, for example. In these cases we'd like to show that the function was never called, which is trivially true. llvm-svn: 229717
* Adding implementation to outline C++ catch handlers for native Windows 64 ↵Andrew Kaylor2015-02-182-127/+484
| | | | | | | | exception handling. Differential Revision: http://reviews.llvm.org/D7363 llvm-svn: 229715
* InstrProf: Make CoverageMapping testable and add a basic unit testJustin Bogner2015-02-181-1/+1
| | | | | | | | Make CoverageMapping easier to create, so that we can write targeted unit tests for its internals, and add a some infrastructure to write these tests. Finally, add a simple unit test for basic functionality. llvm-svn: 229709
* [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generatorJozef Kolek2015-02-182-3/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D7609 llvm-svn: 229706
* [mips][microMIPS] Implement JALX instructionJozef Kolek2015-02-182-2/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D5047 llvm-svn: 229702
* [mips] Add backend support for Mips32r[35] and Mips64r[35].Daniel Sanders2015-02-187-9/+124
| | | | | | | | | | | | | | | | | Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
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