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| author | Marek Olsak <marek.olsak@amd.com> | 2015-02-18 22:12:45 +0000 |
|---|---|---|
| committer | Marek Olsak <marek.olsak@amd.com> | 2015-02-18 22:12:45 +0000 |
| commit | 9b8f32eed15a6e2a7746c1e1ae65a6346d931ff3 (patch) | |
| tree | 6027aa1fad99cccc352abe366a35ea380889b09a /llvm/lib | |
| parent | 8eeebcccb54906ed9f76b633adeb78a0254cd84c (diff) | |
| download | bcm5719-llvm-9b8f32eed15a6e2a7746c1e1ae65a6346d931ff3.tar.gz bcm5719-llvm-9b8f32eed15a6e2a7746c1e1ae65a6346d931ff3.zip | |
R600/SI: Fix READLANE and WRITELANE lane select for VI
VOP2 declares vsrc1, but VOP3 declares src1.
We can't use the same "ins" if the operands have different names in VOP2
and VOP3 encodings.
This fixes a hang in geometry shaders which spill M0 on VI.
(BTW it doesn't look like M0 needs spilling and the spilling seems
duplicated 3 times)
llvm-svn: 229752
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrFormats.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/R600/SIInstrFormats.td b/llvm/lib/Target/R600/SIInstrFormats.td index 816e6b41be1..d376b85dc70 100644 --- a/llvm/lib/Target/R600/SIInstrFormats.td +++ b/llvm/lib/Target/R600/SIInstrFormats.td @@ -289,10 +289,10 @@ class VOP1e <bits<8> op> : Enc32 { class VOP2e <bits<6> op> : Enc32 { bits<8> vdst; bits<9> src0; - bits<8> vsrc1; + bits<8> src1; let Inst{8-0} = src0; - let Inst{16-9} = vsrc1; + let Inst{16-9} = src1; let Inst{24-17} = vdst; let Inst{30-25} = op; let Inst{31} = 0x0; //encoding diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index 4c60647995d..2c28e03af88 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -1533,16 +1533,16 @@ defm V_READLANE_B32 : VOP2SI_3VI_m < vop3 <0x001, 0x289>, "v_readlane_b32", (outs SReg_32:$vdst), - (ins VGPR_32:$src0, SSrc_32:$vsrc1), - "v_readlane_b32 $vdst, $src0, $vsrc1" + (ins VGPR_32:$src0, SCSrc_32:$src1), + "v_readlane_b32 $vdst, $src0, $src1" >; defm V_WRITELANE_B32 : VOP2SI_3VI_m < vop3 <0x002, 0x28a>, "v_writelane_b32", (outs VGPR_32:$vdst), - (ins SReg_32:$src0, SSrc_32:$vsrc1), - "v_writelane_b32 $vdst, $src0, $vsrc1" + (ins SReg_32:$src0, SCSrc_32:$src1), + "v_writelane_b32 $vdst, $src0, $src1" >; // These instructions only exist on SI and CI |
