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| author | Eric Christopher <echristo@gmail.com> | 2015-02-19 01:10:55 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2015-02-19 01:10:55 +0000 |
| commit | 0795a2ef0c4f0f5c23ec674a4da207e3df76dff7 (patch) | |
| tree | d56ccb1a71dc05fc3a7f82317c69d508e4381dcc /llvm/lib | |
| parent | 7edca437f52b1b5d34568f54141aa588335b170f (diff) | |
| download | bcm5719-llvm-0795a2ef0c4f0f5c23ec674a4da207e3df76dff7.tar.gz bcm5719-llvm-0795a2ef0c4f0f5c23ec674a4da207e3df76dff7.zip | |
Remove a few more calls to TargetMachine::getSubtarget from the
R600 port.
llvm-svn: 229804
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/R600MachineScheduler.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIMachineFunctionInfo.cpp | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/R600/R600MachineScheduler.cpp b/llvm/lib/Target/R600/R600MachineScheduler.cpp index a31168ba677..bcde5fb50da 100644 --- a/llvm/lib/Target/R600/R600MachineScheduler.cpp +++ b/llvm/lib/Target/R600/R600MachineScheduler.cpp @@ -26,7 +26,7 @@ using namespace llvm; void R600SchedStrategy::initialize(ScheduleDAGMI *dag) { assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness"); DAG = static_cast<ScheduleDAGMILive*>(dag); - const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>(); + const AMDGPUSubtarget &ST = DAG->MF.getSubtarget<AMDGPUSubtarget>(); TII = static_cast<const R600InstrInfo*>(DAG->TII); TRI = static_cast<const R600RegisterInfo*>(DAG->TRI); VLIW5 = !ST.hasCaymanISA(); diff --git a/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp b/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp index 198dd568374..587ea63d679 100644 --- a/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp @@ -39,8 +39,8 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg( unsigned FrameIndex, unsigned SubIdx) { const MachineFrameInfo *FrameInfo = MF->getFrameInfo(); - const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo*>( - MF->getTarget().getSubtarget<AMDGPUSubtarget>().getRegisterInfo()); + const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( + MF->getSubtarget<AMDGPUSubtarget>().getRegisterInfo()); MachineRegisterInfo &MRI = MF->getRegInfo(); int64_t Offset = FrameInfo->getObjectOffset(FrameIndex); Offset += SubIdx * 4; @@ -70,7 +70,7 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg( unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize( const MachineFunction &MF) const { - const AMDGPUSubtarget &ST = MF.getTarget().getSubtarget<AMDGPUSubtarget>(); + const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>(); // FIXME: We should get this information from kernel attributes if it // is available. return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize(); |
