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* Split several PPC instruction classes.Hal Finkel2012-08-289-102/+269
| | | | | | | | | | | | | Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. llvm-svn: 162729
* Fix bug 13532.Akira Hatanaka2012-08-281-1/+1
| | | | | | | | | In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without using any f64 operations if f64 is not a legal type. Patch by Stefan Kristiansson. llvm-svn: 162728
* Allow remat of LI on PPC.Hal Finkel2012-08-282-1/+3
| | | | | | | | | | | Allow load-immediates to be rematerialised in the register coalescer for PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail, because it relies on a register move getting emitted. The immediate load is equivalent, so change this test case. Patch by Tobias von Koch. llvm-svn: 162727
* Add the Freescale vendor to Triple.Hal Finkel2012-08-281-0/+2
| | | | | | | | | Adds the vendor 'fsl' (used by Freescale SDK) to Triple. This will allow clang support for Freescale cross-compile configurations. Patch by Tobias von Koch. llvm-svn: 162726
* Eliminate redundant CR moves on PPC32.Hal Finkel2012-08-283-8/+34
| | | | | | | | | | | | | | | | The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. llvm-svn: 162725
* Optimize zext on PPC64.Hal Finkel2012-08-281-0/+9
| | | | | | | | | | The zeroextend IR instruction is lowered to an 'and' node with an immediate mask operand, which in turn gets legalised to a sequence of ori's & ands. This can be done more efficiently using the rldicl instruction. Patch by Tobias von Koch. llvm-svn: 162724
* More missing mayLoad flags on AVX multiclasses.Jakob Stoklund Olesen2012-08-281-3/+3
| | | | llvm-svn: 162714
* Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen2012-08-276-43/+169
| | | | | | | | | | | It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. llvm-svn: 162713
* Fix compile error when building with C++11 - clang thinks that PRIx64 is a ↵Marshall Clow2012-08-271-2/+2
| | | | | | user-defined suffix or something llvm-svn: 162704
* Make sure we add the predicate after all of the registers are added.Bill Wendling2012-08-271-2/+3
| | | | | | <rdar://problem/12183003> llvm-svn: 162703
* Don't use for loops for code that is only intended to execute once. NoDan Gohman2012-08-271-6/+6
| | | | | | intended functionality change. Thanks to Ahmed Charles for spotting it. llvm-svn: 162686
* Fix comment.Rafael Espindola2012-08-271-3/+4
| | | | llvm-svn: 162678
* Fix comment for function RuntimeDyldImpl.resolveRelocation()Danil Malyshev2012-08-271-1/+4
| | | | llvm-svn: 162677
* Remove the the block_node_iterator of Region, replace it by the block_iterator.Hongbin Zheng2012-08-272-24/+5
| | | | llvm-svn: 162672
* DWARFDebugRangeList.cpp: Use PRIx64 for uint64_t as format string.NAKAMURA Takumi2012-08-271-2/+3
| | | | llvm-svn: 162665
* Remove MMX shift intrinsic handling code that also exists in ↵Craig Topper2012-08-271-56/+0
| | | | | | SelectionDAGBuilder. llvm-svn: 162661
* [DebugInfo] fixup for r162657: update CMakeLists.txtAlexey Samsonov2012-08-271-0/+1
| | | | llvm-svn: 162659
* Don't allow vextractf128 to be folded with unaligned stores. We don't fold ↵Craig Topper2012-08-271-13/+9
| | | | | | unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur. llvm-svn: 162658
* Add basic support for .debug_ranges section to LLVM's DebugInfo library.Alexey Samsonov2012-08-275-5/+136
| | | | | | | | | | | This section (introduced in DWARF-3) is used to define instruction address ranges for functions that are not contiguous and can't be described by low_pc/high_pc attributes (this is the usual case for inlined subroutines). The patch is the first step to support fetching complete inlining info from DWARF. Reviewed by Benjamin Kramer. llvm-svn: 162657
* Fold some patterns into instruction definitons so tablegen can infer flags ↵Craig Topper2012-08-271-4/+4
| | | | | | removing the need for an explicit 'neverHasSideEffects = 1' llvm-svn: 162656
* Add HasAVX1Only predicate and use it for patterns that have an AVX1 ↵Craig Topper2012-08-272-48/+62
| | | | | | instruction and an AVX2 instruction rather than relying on AddedComplexity. llvm-svn: 162654
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-2412-34/+29
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Add missing mayLoad flags to a large class of AVX *_Int instructions.Jakob Stoklund Olesen2012-08-241-1/+2
| | | | llvm-svn: 162622
* Missed tLEApcrelJT.Jakob Stoklund Olesen2012-08-241-0/+1
| | | | | | | ARMConstantIslandPass expects this instruction to stay in the same basic block as the jump table branch. llvm-svn: 162615
* Explicitly mark LEApcrel pseudos with hasSideEffects.Jakob Stoklund Olesen2012-08-242-0/+4
| | | | | | | | | | It's not clear that they should be marked as such, but tbb formation fails if t2LEApcrelJT is hoisted of of a loop. This doesn't change the flags on these instructions, UnmodeledSideEffects was already inferred from the missing pattern. llvm-svn: 162603
* Fix call instruction operands in ARMFastISel.Jakob Stoklund Olesen2012-08-241-34/+16
| | | | | | | | | The ARM BL and BLX instructions don't have predicate operands, but the thumb variants tBL and tBLX do. The argument registers should be added as implicit uses. llvm-svn: 162593
* Mark X86::RET and RETI instructions as variadic.Jakob Stoklund Olesen2012-08-241-2/+5
| | | | | | | There is special magic happening when returning floating point values on the x87 stack. The RET instructions get extra f80 operands. llvm-svn: 162592
* Avoid including explicit uses when counting SDNode imp-uses.Jakob Stoklund Olesen2012-08-241-3/+6
| | | | | | | It is legal to have a register node as an explicit operand, it shouldn't be counted as an implicit use. llvm-svn: 162591
* Disable Mips' delay slot filler when optimization level is O0.Akira Hatanaka2012-08-241-1/+3
| | | | llvm-svn: 162589
* In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if itsAkira Hatanaka2012-08-241-2/+3
| | | | | | second operand is MipsISD::GPRel. llvm-svn: 162584
* BranchProb: modify the definition of an edge in BranchProbabilityInfo to handleManman Ren2012-08-244-85/+137
| | | | | | | | | | | | | | the case of multiple edges from one block to another. A simple example is a switch statement with multiple values to the same destination. The definition of an edge is modified from a pair of blocks to a pair of PredBlock and an index into the successors. Also set the weight correctly when building SelectionDAG from LLVM IR, especially when converting a Switch. IntegersSubsetMapping is updated to calculate the weight for each cluster. llvm-svn: 162572
* [asan/tsan] rename FunctionBlackList* to BlackList* as this class is not ↵Kostya Serebryany2012-08-245-17/+17
| | | | | | limited to functions any more llvm-svn: 162566
* [asan/tsan] extend the functionality of FunctionBlackList to globals and ↵Kostya Serebryany2012-08-242-55/+89
| | | | | | modules. Patch by Reid Watson. llvm-svn: 162565
* Lower constant pools and jump tables via TOC on PPC64/SVR4.Roman Divacky2012-08-244-8/+42
| | | | | | In collaboration with Adhemerval Zanella. llvm-svn: 162562
* GVN: Fix quadratic runtime on the number of switch cases.Benjamin Kramer2012-08-241-2/+10
| | | | | | | | No intended behavior change. This was introduced in r162023. With the fixed algorithm a Release build of ARMInstPrinter.cpp goes from 16s to 10s on a 2011 MBP. llvm-svn: 162559
* Fix load/store SDNode flags.Jakob Stoklund Olesen2012-08-241-2/+2
| | | | llvm-svn: 162558
* Add missing SDNPSideEffect flags.Jakob Stoklund Olesen2012-08-243-11/+17
| | | | llvm-svn: 162557
* Remove more mayLoad workarounds.Jakob Stoklund Olesen2012-08-241-7/+7
| | | | llvm-svn: 162556
* Custom lower FMA intrinsics to target specific nodes and remove the patterns.Craig Topper2012-08-243-132/+73
| | | | llvm-svn: 162534
* Use DW_FORM_flag_present to save space in debug information if we'reEric Christopher2012-08-244-25/+41
| | | | | | | | not in darwin gdb compat mode. Fixes rdar://10975088 llvm-svn: 162526
* Add support for some missing DW_FORM_*.Eric Christopher2012-08-242-0/+77
| | | | | TODO: Fix code duplication and coding style. llvm-svn: 162525
* Formatting.Eric Christopher2012-08-241-1/+1
| | | | llvm-svn: 162524
* Fix undefined behavior (negation of INT_MIN) in ARM backend.Richard Smith2012-08-242-2/+2
| | | | llvm-svn: 162520
* Fix floating-point divide by zero, in a case where the value was not going ↵Richard Smith2012-08-241-1/+1
| | | | | | to be used anyway. llvm-svn: 162518
* Remove some spurious mayLoad = 0 flags.Jakob Stoklund Olesen2012-08-241-14/+8
| | | | | | | They were inserted to silence TableGen's warning about redundant properties. That warning is now gone. llvm-svn: 162517
* Add missing SDNP properties on the flushw node.Jakob Stoklund Olesen2012-08-241-1/+1
| | | | llvm-svn: 162515
* X86MemBarrier has unmodeled side effects.Jakob Stoklund Olesen2012-08-241-1/+1
| | | | llvm-svn: 162514
* Fix undefined behavior (signed integer overflow) when Clang parses a ↵Richard Smith2012-08-241-1/+3
| | | | | | hexfloat with an enormous exponent. Caught by an existing unit test + -ftrapv. llvm-svn: 162505
* Formatting cleanup.Eric Christopher2012-08-231-7/+7
| | | | llvm-svn: 162499
* Add an assert here in case parsing gave us a NULL compile unit.Eric Christopher2012-08-231-1/+3
| | | | llvm-svn: 162498
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