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| author | Bill Wendling <isanbard@gmail.com> | 2012-08-27 22:12:44 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2012-08-27 22:12:44 +0000 |
| commit | 988a47d7e558c398552c5b867df0639349be3e3e (patch) | |
| tree | 34331d2853918bc0094e1d43d89437d96bde678f /llvm/lib | |
| parent | 29f9a00732f5a0d3f147d71b2d51270bcfe02f16 (diff) | |
| download | bcm5719-llvm-988a47d7e558c398552c5b867df0639349be3e3e.tar.gz bcm5719-llvm-988a47d7e558c398552c5b867df0639349be3e3e.zip | |
Make sure we add the predicate after all of the registers are added.
<rdar://problem/12183003>
llvm-svn: 162703
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 29033e5117f..2112992dd86 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -712,11 +712,12 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing); unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); assert(Dst && Src && "Bad sub-register"); - Mov = AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) - .addReg(Src)); + Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) + .addReg(Src); // VORR takes two source operands. if (Opc == ARM::VORRq) Mov.addReg(Src); + Mov = AddDefaultPred(Mov); } // Add implicit super-register defs and kills to the last instruction. Mov->addRegisterDefined(DestReg, TRI); |
