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* [PowerPC] Add subregister classes for f64 VSX valuesHal Finkel2014-03-298-59/+192
| | | | | | | | | | | | | We had stored both f64 values and v2f64, etc. values in the VSX registers. This worked, but was suboptimal because we would always spill 16-byte values even through we almost always had scalar 8-byte values. This resulted in an increase in stack-size use, extra memory bandwidth, etc. To fix this, I've added 64-bit subregisters of the Altivec registers, and combined those with the existing scalar floating-point registers to form a class of VSX scalar floating-point registers. The ABI code has also been enhanced to use this register class and some other necessary improvements have been made. llvm-svn: 205075
* Windows: canonicalise the default windows tripleSaleem Abdulrasool2014-03-291-1/+1
| | | | | | | Canonicalise the default triple that is used on Windows. This should hopefully fix the MSVC buildbots. llvm-svn: 205070
* [x86] Fix printing of register operands with q modifier.Akira Hatanaka2014-03-281-3/+5
| | | | | | | | | Emit 32-bit register names instead of 64-bit register names if the target does not have 64-bit general purpose registers. <rdar://problem/14653996> llvm-svn: 205067
* Debug Compression: Avoid compression debug_frame for nowDavid Blaikie2014-03-281-1/+1
| | | | | | | | Turns out debug_frame does use multiple fragments, so it doesn't compress correctly with the current approach. Disable compressing it for now while I figure out what's the best solution for it. llvm-svn: 205059
* X86: Disable IsLegalToCallImmediateAddr for Win32David Majnemer2014-03-281-1/+4
| | | | | | | | | | WinCOFF cannot form PC relative relocations to support absolute MCValues. We should reenable this once WinCOFF supports emission of IMAGE_REL_I386_REL32 relocations. This fixes PR19272. llvm-svn: 205058
* [PowerPC] Fix VSX permutation iselHal Finkel2014-03-281-1/+1
| | | | | | | Not only did I invert the indices when I wrote the code, but I also did the same thing when I wrote the regression test. Oops. llvm-svn: 205046
* [PowerPC] v2[fi]64 need to be explicitly passed in VSX registersHal Finkel2014-03-282-7/+36
| | | | | | | | v2[fi]64 values need to be explicitly passed in VSX registers. This is because the code in TRI that finds the minimal register class given a register and a value type will assert if given an Altivec register and a non-Altivec type. llvm-svn: 205041
* Map ELf flags back to more specific section kinds.Rafael Espindola2014-03-281-2/+28
| | | | | | With that, convert another llc -filetype=obj test. llvm-svn: 205031
* Parse .gpdword and convert another llc -filetype=obj test.Rafael Espindola2014-03-281-1/+22
| | | | llvm-svn: 205028
* SLPVectorizer: Take credit for free extractelement instructionsArnold Schwaighofer2014-03-281-2/+11
| | | | | | | | | Extract element instructions that will be removed when vectorzing lower the cost. Patch by Arch D. Robison! llvm-svn: 205020
* SLPVectorizer: Fix typosArnold Schwaighofer2014-03-281-2/+2
| | | | | | Patch by Arch D. Robison! llvm-svn: 205019
* SLPVectorizer: Ignore users that are insertelements we can reschedule themArnold Schwaighofer2014-03-281-30/+65
| | | | | | Patch by Arch D. Robison! llvm-svn: 205018
* Add const to a method I missed in the previous commit.Rafael Espindola2014-03-281-7/+4
| | | | llvm-svn: 205014
* Add const.Rafael Espindola2014-03-284-7/+8
| | | | llvm-svn: 205013
* Revert "InstCombine: merge constants in both operands of icmp."Erik Verbruggen2014-03-282-14/+12
| | | | | | | | | This reverts commit r204912, and follow-up commit r204948. This introduced a performance regression, and the fix is not completely clear yet. llvm-svn: 205010
* Revert "GVN: merge overflow intrinsics with non-overflow instructions."Erik Verbruggen2014-03-281-124/+58
| | | | | | | | | This reverts commit r203553, and follow-up commits r203558 and r203574. I will follow this up on the mailinglist to do it in a way that won't cause subtle PRE bugs. llvm-svn: 205009
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-2818-87/+431
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 llvm-svn: 205007
* R600: avoid calling std::next on an iterator that might be end()Tim Northover2014-03-281-3/+3
| | | | | | | | This was causing my llc to go into an infinite loop on CodeGen/R600/address-space.ll (just triggered recently by some allocator changes). llvm-svn: 205005
* Intrinsics: expand semantics of LLVMExtendedVectorType (& trunc)Tim Northover2014-03-282-22/+48
| | | | | | | | | | | | These are used in the ARM backends to aid type-checking on patterns involving intrinsics. By making sure one argument is an extended/truncated version of another. However, there's no reason to limit them to just vectors types. For example AArch64 has the instruction "uqshrn sD, dN, #imm" which would naturally use an intrinsic taking an i64 and returning an i32. llvm-svn: 205003
* [Allocator Cleanup] Move generic pointer alignment helper out of anChandler Carruth2014-03-281-15/+3
| | | | | | | out-of-line private static method and into the collection of inline alignment helpers in MathExtras.h. llvm-svn: 204995
* [Allocator Cleanup] Make the growth of the "slab" size of theChandler Carruth2014-03-281-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | BumpPtrAllocator significantly less strange by making it a simple function of the number of slabs allocated rather than by making it a recurrance. I *think* the previous behavior was essentially that the size of the slabs would be doubled after the first 128 were allocated, and then doubled again each time 64 more were allocated, but only if every allocation packed perfectly into the slab size. If not, the wasted space wouldn't be counted toward increasing the size, but allocations over the size threshold *would*. And since the allocations over the size threshold might be much larger than the slab size, this could have somewhat surprising consequences where we rapidly grow the slab size. This currently requires adding state to the allocator to track the number of slabs currently allocated, but that isn't too bad. I'm planning further changes to the allocator that will make this state fall out even more naturally. It still doesn't fully decouple the growth rate from the allocations which are over the size threshold. That fix is coming later. This specific fix will allow making the entire thing into a more stateless device and lifting the parameters into template parameters rather than runtime parameters. llvm-svn: 204993
* [cleanup] Hoist the initialization and constants for slab sizes to theChandler Carruth2014-03-281-20/+17
| | | | | | | | top of the default jit memory manager. This will allow them to be used as template parameters rather than runtime parameters in a subsequent commit. llvm-svn: 204992
* C++11: convert verbose loops to range-based loops.Adrian Prantl2014-03-271-7/+6
| | | | llvm-svn: 204981
* [PowerPC] Use a small cleanup pass to remove VSX self copiesHal Finkel2014-03-273-0/+78
| | | | | | | | | | | | As explained in r204976, because of how the allocation of VSX registers interacts with the call-lowering code, we sometimes end up generating self VSX copies. Specifically, things like this: %VSL2<def> = COPY %F2, %VSL2<imp-use,kill> (where %F2 is really a sub-register of %VSL2, and so this copy is a nop) This adds a small cleanup pass to remove these prior to post-RA scheduling. llvm-svn: 204980
* Provide a target override for the cost of using a callee-saved registerManman Ren2014-03-271-2/+6
| | | | | | | | | for the first time. Thanks Andy for the discussion. rdar://16162005 llvm-svn: 204979
* Canonicalise Windows target triple spellingsSaleem Abdulrasool2014-03-275-8/+35
| | | | | | | | | | | | | | | | | | | | | | | | | Construct a uniform Windows target triple nomenclature which is congruent to the Linux counterpart. The old triples are normalised to the new canonical form. This cleans up the long-standing issue of odd naming for various Windows environments. There are four different environments on Windows: MSVC: The MS ABI, MSVCRT environment as defined by Microsoft GNU: The MinGW32/MinGW32-W64 environment which uses MSVCRT and auxiliary libraries Itanium: The MSVCRT environment + libc++ built with Itanium ABI Cygnus: The Cygwin environment which uses custom libraries for everything The following spellings are now written as: i686-pc-win32 => i686-pc-windows-msvc i686-pc-mingw32 => i686-pc-windows-gnu i686-pc-cygwin => i686-pc-windows-cygnus This should be sufficiently flexible to allow us to target other windows environments in the future as necessary. llvm-svn: 204977
* [PowerPC] Don't remove self VSX copies in PPCInstrInfo::copyPhysRegHal Finkel2014-03-271-9/+13
| | | | | | | | | | | | | | | Because of how the allocation of VSX registers interacts with the call-lowering code, we sometimes end up generating self VSX copies. Specifically, things like this: %VSL2<def> = COPY %F2, %VSL2<imp-use,kill> (where %F2 is really a sub-register of %VSL2, and so this copy is a nop) The problem is that ExpandPostRAPseudos always assumes that *some* instruction has been inserted, and adds implicit defs to it. This is a problem if no copy was inserted because it can cause subtle problems during post-RA scheduling. These self copies will have to be removed some other way. llvm-svn: 204976
* [X86][Vector Cost Model] Add a comment to explain the workaroundQuentin Colombet2014-03-271-0/+5
| | | | | | | | in my previous commit (r204884). <rdar://problem/16381225> llvm-svn: 204972
* [PowerPC] Fix v2f64 vector extract and related patternsHal Finkel2014-03-272-4/+4
| | | | | | | | | First, v2f64 vector extract had not been declared legal (and so the existing patterns were not being used). Second, the patterns for that, and for scalar_to_vector, should really be a regclass copy, not a subregister operation, because the VSX registers directly hold both the vector and scalar data. llvm-svn: 204971
* [PowerPC] Expand v2i64 shiftsHal Finkel2014-03-271-0/+4
| | | | | | | | These operations need to be expanded during legalization so that isel does not crash. In theory, we might be able to custom lower some of these. That, however, would need to be follow-up work. llvm-svn: 204963
* Register Allocator: refactoring and add comments.Manman Ren2014-03-271-35/+58
| | | | | | | | No functionality change. Thanks Andy for reviewing. rdar://16162005 llvm-svn: 204962
* Remove another unused argument.Rafael Espindola2014-03-279-28/+20
| | | | llvm-svn: 204961
* DebugInfo: Support for compressed debug info sectionsDavid Blaikie2014-03-274-8/+67
| | | | | | | | | | | | | | | | | | | 1) When creating a .debug_* section and instead create a .zdebug_ section. 2) When creating a fragment in a .zdebug_* section, make it a compressed fragment. 3) When computing the size of a compressed section, compress the data and use the size of the compressed data. 4) Emit the compressed bytes. Also, check that only if a section has a compressed fragment, then that is the only fragment in the section. Assert-fail if the fragment's data is modified after it is compressed. Initial review on llvm-commits by Eric Christopher and Rafael Espindola. llvm-svn: 204958
* DebugInfo: TargetOptions/MCAsmInfo support for compressed debug info sectionsDavid Blaikie2014-03-271-0/+3
| | | | llvm-svn: 204957
* Remove unused argument.Rafael Espindola2014-03-279-41/+24
| | | | llvm-svn: 204956
* InstCombine: Don't combine constants on unsigned icmpsReid Kleckner2014-03-271-1/+2
| | | | | | | | | Fixes a miscompile introduced in r204912. It would miscompile code like (unsigned)(a + -49) <= 5U. The transform would turn this into (unsigned)a < 55U, which would return true for values in [0, 49], when it should not. llvm-svn: 204948
* R600: Implement isZExtFree.Matt Arsenault2014-03-272-0/+20
| | | | | | | This allows 64-bit operations that are truncated to be reduced to 32-bit ones. llvm-svn: 204946
* R600/SI: Fix unreachable with a sext_in_reg to an illegal type.Matt Arsenault2014-03-274-4/+28
| | | | llvm-svn: 204945
* [mips] Some uses of isMips64()/hasMips64() are really tests for 64-bit GPR'sDaniel Sanders2014-03-276-23/+23
| | | | | | | | | | | | Summary: No functional change since these predicates are (currently) synonymous. Extracted from a patch by David Chisnall His work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3202 llvm-svn: 204943
* [AArch64] Lower SHL_PARTS, SRA_PARTS and SRL_PARTSLogan Chien2014-03-272-0/+91
| | | | | | | | Lower SHL_PARTS, SRA_PARTS and SRL_PARTS to perform 128-bit integer shift Patch by GuanHong Liu. llvm-svn: 204940
* Prevent alias from pointing to weak aliases.Rafael Espindola2014-03-2712-41/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds back r204781. Original message: Aliases are just another name for a position in a file. As such, the regular symbol resolutions are not applied. For example, given define void @my_func() { ret void } @my_alias = alias weak void ()* @my_func @my_alias2 = alias void ()* @my_alias We produce without this patch: .weak my_alias my_alias = my_func .globl my_alias2 my_alias2 = my_alias That is, in the resulting ELF file my_alias, my_func and my_alias are just 3 names pointing to offset 0 of .text. That is *not* the semantics of IR linking. For example, linking in a @my_alias = alias void ()* @other_func would require the strong my_alias to override the weak one and my_alias2 would end up pointing to other_func. There is no way to represent that with aliases being just another name, so the best solution seems to be to just disallow it, converting a miscompile into an error. llvm-svn: 204934
* [mips] Attempting to use register $32 should be an error instead of an ↵Daniel Sanders2014-03-271-1/+1
| | | | | | | | | | | | assertion. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3201 llvm-svn: 204932
* The forward declare should be a struct instead of a class (to be consistent ↵Aaron Ballman2014-03-271-1/+1
| | | | | | with the definition, as well as to silence an MSVC C4099 warning). llvm-svn: 204928
* [mips] Add support for .cpsetupDaniel Sanders2014-03-271-0/+133
| | | | | | | | | | | | | | Summary: Patch by Robert N. M. Watson His work was sponsored by: DARPA, AFRL Small corrections by myself. CC: theraven, matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3199 llvm-svn: 204924
* [mips] The decision between GOT_DISP and GOT16 for global addresses depends ↵Daniel Sanders2014-03-271-2/+2
| | | | | | | | | | | | | | on ABI rather than MIPS64 Summary: No functional change (for supported use cases) Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3191 llvm-svn: 204922
* Split the file MipsAsmBackend.cpp in Split the file MipsAsmBackend.cpp and ↵Zoran Jovanovic2014-03-272-195/+241
| | | | | | | | Split the file MipsAsmBackend.h. Differential Revision: http://llvm-reviews.chandlerc.com/D3134 llvm-svn: 204921
* All new elements except the last one initialized to NULL. Ideally, once ↵Karthik Bhat2014-03-271-7/+7
| | | | | | | | | parsing is complete, all elements should be non-NULL. To safe-guard BitcodeReader, this patch adds null check for all access to these list. Patch by Dinesh Dwivedi! llvm-svn: 204920
* [mips] Remove unused private field.Matheus Almeida2014-03-271-2/+1
| | | | llvm-svn: 204919
* [mips] NaCl should now use the custom MipsELFStreamer (recently added) in spiteMatheus Almeida2014-03-273-14/+18
| | | | | | | | | | | | | | of MCELFStreamer. This is so that changes to MipsELFStreamer will automatically propagate through its subclasses. No functional changes (MipsELFStreamer has the same functionality of MCELFStreamer at the moment). Differential Revision: http://llvm-reviews.chandlerc.com/D3130 llvm-svn: 204918
* [mips] Implement custom MCELFStreamer.Matheus Almeida2014-03-274-1/+66
| | | | | | | | | | | | | This allows us to insert some hooks before emitting data into an actual object file. For example, we can capture the register usage for a translation unit by overriding the EmitInstruction method. The register usage information is needed to generate .reginfo and .Mips.options ELF sections. No functional changes. Differential Revision: http://llvm-reviews.chandlerc.com/D3129 llvm-svn: 204917
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