R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies

llvm-svn: 205732

2 files changed, 12 insertions, 0 deletions

diff --git a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp
index 402f1f4d651..29d154ff425 100644
--- a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp
@@ -256,6 +256,16 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
         TII->moveToVALU(MI);
         break;
       }
+      case AMDGPU::INSERT_SUBREG: {
+        const TargetRegisterClass *DstRC, *SrcRC;
+        DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
+        SrcRC = MRI.getRegClass(MI.getOperand(1).getReg());
+        if (!TRI->isSGPRClass(DstRC) || !TRI->hasVGPRs(SrcRC))
+          break;
+        DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n");
+        DEBUG(MI.print(dbgs()));
+        TII->moveToVALU(MI);
+      }
       }
     }
   }
diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp
index ab2fe093172..b19ff98bed7 100644
--- a/llvm/lib/Target/R600/SIInstrInfo.cpp
+++ b/llvm/lib/Target/R600/SIInstrInfo.cpp
@@ -516,6 +516,7 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
   case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
   case AMDGPU::COPY: return AMDGPU::COPY;
   case AMDGPU::PHI: return AMDGPU::PHI;
+  case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
   case AMDGPU::S_MOV_B32:
     return MI.getOperand(1).isReg() ?
            AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
@@ -996,6 +997,7 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
     case AMDGPU::COPY:
     case AMDGPU::PHI:
     case AMDGPU::REG_SEQUENCE:
+    case AMDGPU::INSERT_SUBREG:
       if (RI.hasVGPRs(NewDstRC))
         continue;
       NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);