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| author | Hal Finkel <hfinkel@anl.gov> | 2014-03-27 22:22:48 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2014-03-27 22:22:48 +0000 |
| commit | 82569b63666d9605bae5257b6492a9015eb07ac9 (patch) | |
| tree | 9d68077d662da377691469594b9f569eef1d2a0b /llvm/lib | |
| parent | e93efaa0e18bbb68b5d7f79d8018dcaa561e891f (diff) | |
| download | bcm5719-llvm-82569b63666d9605bae5257b6492a9015eb07ac9.tar.gz bcm5719-llvm-82569b63666d9605bae5257b6492a9015eb07ac9.zip | |
[PowerPC] Fix v2f64 vector extract and related patterns
First, v2f64 vector extract had not been declared legal (and so the existing
patterns were not being used). Second, the patterns for that, and for
scalar_to_vector, should really be a regclass copy, not a subregister
operation, because the VSX registers directly hold both the vector and scalar data.
llvm-svn: 204971
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 7 |
2 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 16ff0eb7d72..1c19160c9c6 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -535,6 +535,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) if (Subtarget->hasVSX()) { setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 643ba1fbb02..1ece55977a1 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -724,13 +724,12 @@ def : InstAlias<"xxswapd $XT, $XB", let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns. def : Pat<(v2f64 (scalar_to_vector f64:$A)), - (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), $A, sub_64)>; + (v2f64 (COPY_TO_REGCLASS $A, VSRC))>; def : Pat<(f64 (vector_extract v2f64:$S, 0)), - (EXTRACT_SUBREG (v2f64 (COPY_TO_REGCLASS $S, VSLRC)), sub_64)>; + (f64 (COPY_TO_REGCLASS $S, VSRC))>; def : Pat<(f64 (vector_extract v2f64:$S, 1)), - (EXTRACT_SUBREG (v2f64 (COPY_TO_REGCLASS (XXPERMDI $S, $S, 3), - VSLRC)), sub_64)>; + (f64 (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSRC))>; // Additional fnmsub patterns: -a*c + b == -(a*c - b) def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), |
