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* | -> ||Richard Trieu2014-09-171-1/+1
| | | | | | No functional change. llvm-svn: 217934
* Fix identify_magic() with mach-o stub dylibs.Nick Kledzik2014-09-171-1/+1
| | | | | | The wrong value was returned and the unittest did not cover the stub dylib case. llvm-svn: 217933
* [llvm-objdump] properly use c_str() with format("%s"). Improve ↵Nick Kledzik2014-09-171-10/+5
| | | | | | getLibraryShortNameByIndex() error handling. llvm-svn: 217930
* [X86] Use the generic AtomicExpandPass instead of X86AtomicExpandPassRobin Morisset2014-09-1711-342/+211
| | | | | | | | | | | | This required a new hook called hasLoadLinkedStoreConditional to know whether to expand atomics to LL/SC (ARM, AArch64, in a future patch Power) or to CmpXchg (X86). Apart from that, the new code in AtomicExpandPass is mostly moved from X86AtomicExpandPass. The main result of this patch is to get rid of that pass, which had lots of code duplicated with AtomicExpandPass. llvm-svn: 217928
* [CodeGenPrepare][AddressingModeMatcher] The promotion mechanism was expectingQuentin Colombet2014-09-161-45/+55
| | | | | | instructions when truncate, sext, or zext were created. Fix that. llvm-svn: 217926
* This add a reset method for WinCOFFObjectWriter, like other MC* classes.Yaron Keren2014-09-161-0/+16
| | | | llvm-svn: 217907
* Add back a fallback case for targets that do not or cannot implement ↵Owen Anderson2014-09-161-1/+5
| | | | | | getNoopForMachoTarget(). llvm-svn: 217899
* Fix typoMatt Arsenault2014-09-161-1/+1
| | | | llvm-svn: 217892
* Add a missing return to operator=Reid Kleckner2014-09-161-0/+1
| | | | llvm-svn: 217889
* Fix move-only type issues in Interpreter with MSVCReid Kleckner2014-09-161-12/+24
| | | | | | | | | MSVC 2012 cannot infer any move special members, but it will call them if available. MSVC 2013 cannot infer move assignment. Therefore, explicitly implement the special members for the ExecutionContext class and its contained types. llvm-svn: 217887
* [TableGen] Fully resolve class-instance values before defs in multiclassesAdam Nemet2014-09-161-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By class-instance values I mean 'Class<Arg>' in 'Class<Arg>.Field' or in 'Other<Class<Arg>>' (syntactically s SimpleValue). This is to differentiate from unnamed/anonymous record definitions (syntactically an ObjectBody) which are not affected by this change. Consider the testcase: class Struct<int i> { int I = !shl(i, 1); int J = !shl(I, 1); } class Class<Struct s> { int Class_J = s.J; } multiclass MultiClass<int i> { def Def : Class<Struct<i>>; } defm Defm : MultiClass<2>; Before this fix, DefmDef.Class_J yields !shl(I, 1) instead of 8. This is the sequence of events. We start with this: multiclass MultiClass<int i> { def Def : Class<Struct<i>>; } During ParseDef the anonymous object for the class-instance value is created: multiclass Multiclass<int i> { def anonymous_0 : Struct<i>; def Def : Class<NAME#anonymous_0>; } Then class Struct<i> is added to anonymous_0. Also Class<NAME#anonymous_0> is added to Def: multiclass Multiclass<int i> { def anonymous_0 { int I = !shl(i, 1); int J = !shl(I, 1); } def Def { int Class_J = NAME#anonymous_0.J; } } So far so good but then we move on to instantiating this in the defm by substituting the template arg 'i'. This is how the anonymous prototype looks after fully instantiating. defm Defm = { def Defmanonymous_0 { int I = 4; int J = !shl(I, 1); } Note that we only resolved the reference to the template arg. The non-template-arg reference in 'J' has not been resolved yet. Then we go on to instantiating the Def prototype: def DefmDef { int Class_J = NAME#anonymous_0.J; } Which is resolved to Defmanonymous_0.J and then to !shl(I, 1). When we fully resolve each record in a defm, Defmanonymous_0.J does get set to 8 but that's too late for its use. The patch adds a new attribute to the Record class that indicates that this def is actually a class-instance value that may be *used* by other defs in a multiclass. (This is unlike regular defs which don't reference each other and thus can be resolved indepedently.) They are then fully resolved before the other defs while the multiclass is instantiated. I added vg_leak to the new test. I am not sure if this is necessary but I don't think I have a way to test it. I can also check in without the XFAIL and let the bots test this part. Also tested that X86.td.expanded and AAarch64.td.expanded were unchange before and after this change. (This issue triggering this problem is a WIP patch.) Part of <rdar://problem/17688758> llvm-svn: 217886
* [X86] Improve commentAdam Nemet2014-09-161-3/+4
| | | | llvm-svn: 217885
* ARM load/store optimizer: Don't materialize a new base register withMoritz Roth2014-09-161-4/+15
| | | | | | | | | | | | | | | | | ADDS/SUBS unless it's safe to clobber the condition flags. If the merged instructions are in a range where the CPSR is live, e.g. between a CMP -> Bcc, we can't safely materialize a new base register. This problem is quite rare, I couldn't come up with a test case and I've never actually seen this happen in the tests I'm running - there is a potential trigger for this in LNT/oggenc (spills being inserted between a CMP/Bcc), but at the moment this isn't being merged. I'll try to reduce that into a small test case once I've committed my upcoming patch to make merging less conservative. llvm-svn: 217881
* Spell out a move ctor. Even the 2013 vintage of MSVC cannot synthesize move ↵Benjamin Kramer2014-09-161-1/+1
| | | | | | ctors. llvm-svn: 217879
* Interpreter: Hack around a series of bugs in MSVC 2012 that copies around thisBenjamin Kramer2014-09-161-3/+9
| | | | | | | | move-only struct. I feel terrible now, but at least it's shielded away from proper compilers. llvm-svn: 217875
* [mips] Improve the error messages given by MipsAsmParser.Toma Tabacu2014-09-161-39/+42
| | | | | | | | | | | | Summary: Changed error messages to be more informative and to resemble other clang/llvm error messages (first letter is lower case, no ending punctuation) and updated corresponding tests. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5065 llvm-svn: 217873
* Make DWARFUnitSection final and change base class to non-virtual protected ↵Frederic Riss2014-09-161-3/+4
| | | | | | | | destructor. As per dblaikie suggestion. llvm-svn: 217871
* [mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to ↵Toma Tabacu2014-09-162-3/+2
| | | | | | | | | | MipsInstrInfo.td. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5244 llvm-svn: 217868
* [mips] Marked the ADDi instruction aliases as not available in Mips32R6 and ↵Toma Tabacu2014-09-162-6/+7
| | | | | | | | | | Mips64R6. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5242 llvm-svn: 217867
* ARMAsmBackend uses a factory method to generate binary file format specificJoe Abbey2014-09-165-245/+341
| | | | | | | | | | | | | | | | | objects. There were a few FIXMEs in ARMAsmBackend.cpp suggesting the class definitions should be in a separate file. Starting with ARMAsmBackend, the class definition has been put in a header file, and #includes reduced. Each sub-type of ARMAsmBackend is now in its own header file. Derived types have been painted with a different color of bike-shed: s/DarwinARMAsmBackend/ARMAsmBackendDarwin/g s/ARMWinCOFFAsmBackend/ARMAsmBackendWinCOFF/g s/ELFARMAsmBackend/ARMAsmBackendELF/g Finally, clang-format has been run across ARMAsmBackend.cpp llvm-svn: 217866
* AVX-512: added cost for some AVX-512 instructionsElena Demikhovsky2014-09-161-0/+62
| | | | llvm-svn: 217863
* Fix BasicTTI::getCmpSelInstrCost to deal with illegal vector typesHal Finkel2014-09-161-1/+2
| | | | | | | | | | | | | | | | | | | The default implementation of getCmpSelInstrCost, which provides the cost of icmp/fcmp/select instructions, did not deal sensibly with illegal vector types that were scalarized. We'd ask for the legalization cost of the vector type, which would return something like (4, f64) given an input of <4 x double>, and we'd then check the TLI status of the ISD opcode on that scalar type. This would result in querying (ISD::VSELECT, f64), for example. Amusingly enough, ISD::VSELECT on scalar types is marked as Legal by default (as with most other operations), and most backends never change this because VSELECT is never generated on scalars. However, seeing the resulting operation as Legal, we'd neglect to add the scalarization cost before returning. The result is that we'd grossly under-estimate the cost of cmps/selects on illegal vector types. Now, if type legalization clearly results in scalarization, we skip the early return and add the scalarization cost. llvm-svn: 217859
* [x86] Remove a FIXME that doesn't make any sense. Only the lanes feedingChandler Carruth2014-09-161-3/+0
| | | | | | | the blend that is matched by this are "used" in any sense, and so any build_vector or other nodes feeding these will already drop other lanes. llvm-svn: 217855
* [x86] Cleanup an unused variable by actually using it in the non-assertsChandler Carruth2014-09-161-1/+1
| | | | | | place where it was needed. llvm-svn: 217854
* [llvm-objdump] for mach-o add -bind, -lazy-bind, and -weak-bind optionsNick Kledzik2014-09-161-1/+281
| | | | | | | | | | | | | | | | This finishes the ability of llvm-objdump to print out all information from the LC_DYLD_INFO load command. The -bind option prints out symbolic references that dyld must resolve immediately. The -lazy-bind option prints out symbolc reference that are lazily resolved on first use. The -weak-bind option prints out information about symbols which dyld must try to coalesce across images. llvm-svn: 217853
* [x86] Remove the last vestiges of the BLENDI-based ADDSUB patternChandler Carruth2014-09-162-50/+10
| | | | | | | | | | | | | matching. This design just fundamentally didn't work because ADDSUB is available prior to any legal lowerings of BLENDI nodes. Instead, we have a dedicated ADDSUB synthetic ISD node which is pattern matched trivially into the instructions. These nodes are then recognized by both the existing and a trivial new lowering combine in the backend. Removing these patterns required adding 2 missing shuffle masks to the DAG combine, without which tests would have failed. Added the masks and a helpful assert as well to catch if anything ever goes wrong here. llvm-svn: 217851
* [FastISel][AArch64] Add vector support to argument lowering.Juergen Ributzka2014-09-161-42/+44
| | | | | | Lower the first 8 vector arguments too. llvm-svn: 217850
* [x86] As a follow-up to r217819, don't check for VSELECT legality nowChandler Carruth2014-09-161-7/+1
| | | | | | | | | | | that we don't use VSELECT and directly emit an addsub synthetic node. Also remove a stale comment referencing VSELECT. The test case is updated to use 'core2' which only has SSE3, not SSE4.1, and it still passes. Previously it would not because we lacked sufficient blend support to legalize the VSELECT. llvm-svn: 217849
* [x86] Add the beginnings of a proper DAG combine to match ADDSUBPS andChandler Carruth2014-09-161-0/+55
| | | | | | | | | | | | | ADDSUBPD nodes out of blends of adds and subs. This allows us to actually form these instructions with SSE3 rather than only forming them when we had both SSE3 for the ADDSUB instructions and SSE4.1 for the blend instructions. ;] Kind-of important. I've adjusted the CPU requirements on one of the tests to demonstrate this kicking in nicely for an SSE3 cpu configuration. llvm-svn: 217848
* [FastISel][AArch64] Allow handling of vectors during return lowering for ↵Juergen Ributzka2014-09-151-2/+7
| | | | | | | | | | little endian machines. Allow handling of vectors during return lowering at least for little endian machines. This was restricted in r208200 to fix it for big endian machines (according to the comment), but it also disabled it for little endian too. llvm-svn: 217846
* [FastISel][AArch64] Update function and variable names to follow the coding ↵Juergen Ributzka2014-09-151-164/+162
| | | | | | standard. NFC. llvm-svn: 217845
* DebugInfo: Add comment describing the need to disable address pool usage in ↵David Blaikie2014-09-151-0/+5
| | | | | | | | skeleton units. Post commit review from Eric Christopher. llvm-svn: 217842
* [FastISel][AArch64] Make AArch64FastISel class final. NFC.Juergen Ributzka2014-09-151-1/+1
| | | | llvm-svn: 217840
* [FastISel][AArch64] Lower sin/cos/pow to runtime lib calls.Juergen Ributzka2014-09-151-0/+50
| | | | | | | | Also lower sin/cos/pow to runtime lib calls. This fixes rdar://problem/18343468. llvm-svn: 217839
* [FastISel][AArch64] Add lowering support for frem.Juergen Ributzka2014-09-151-1/+44
| | | | | | | | | | | This lowers frem to a runtime libcall inside fast-isel. The test case also checks the CallLoweringInfo bug that was exposed by this change. This fixes rdar://problem/18342783. llvm-svn: 217833
* Replace repeated null checks with an assert. NFC.Sanjay Patel2014-09-151-18/+14
| | | | | | | Without a vector to hold the created ops, these functions don't have any use. llvm-svn: 217831
* [FastISel][AArch64] Refactor selectAddSub, selectLogicalOp, and SelectShift. ↵Juergen Ributzka2014-09-151-27/+41
| | | | | | | | NFC. Small refactor to tidy up the code a little. llvm-svn: 217827
* [FastISel][AArch64] Refactor code to use isTypeSupported. NFC.Juergen Ributzka2014-09-151-19/+6
| | | | | | Gets rid of isLoadStoreTypeLegal and replace it with isTypeSupported. llvm-svn: 217826
* Remove dead code in SimplifyCFGJingyue Wu2014-09-151-43/+0
| | | | | | | | | | | | | | | | | | | | | | | Summary: UsedByBranch is always true according to how BonusInst is defined. Test Plan: Passes check-all, and also verified if (BonusInst && !UsedByBranch) { ... } is never entered during check-all. Reviewers: resistor, nadav, jingyue Reviewed By: jingyue Subscribers: llvm-commits, eliben, meheff Differential Revision: http://reviews.llvm.org/D5324 llvm-svn: 217824
* [FastISel][AArch64] Improve floating-point compare support.Juergen Ributzka2014-09-151-7/+62
| | | | | | | | Add support for the last two missing fcmp condition codes: UEQ and ONE. This fixes rdar://problem/18341575. llvm-svn: 217823
* [FastISel] Move optimizeCmpPredicate to FastISel base class. NFC.Juergen Ributzka2014-09-152-40/+40
| | | | | | Make the optimizeCmpPredicate function available to all targets. llvm-svn: 217822
* Add mips32 r1 to the list of supported targets for Mips fast-iselReed Kotler2014-09-151-1/+2
| | | | | | | | | | | | | | | | | | | | | Summary: Expand list of supported targets for Mips to include mips32 r1. Previously it only include r2. More patches are coming where there is a difference but in the current patches as pushed upstream, r1 and r2 are equivalent. Test Plan: simplestorefp1.ll add new build bots at mips to test this flavor at both -O0 and -O2 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5306 llvm-svn: 217821
* Fix the build for MSVC, it doesn't support extended sizeofDavid Majnemer2014-09-151-4/+4
| | | | llvm-svn: 217820
* [x86] Start fixing our emission of ADDSUBPS and ADDSUBPD instructions byChandler Carruth2014-09-154-26/+37
| | | | | | | | | | | | | | | | introducing a synthetic X86 ISD node representing this generic operation. The relevant patterns for mapping these nodes into the concrete instructions are also added, and a gnarly bit of C++ code in the target-specific DAG combiner is replaced with simple code emitting this primitive. The next step is to generically combine blends of adds and subs into this node so that we can drop the reliance on an SSE4.1 ISD node (BLENDI) when matching an SSE3 feature (ADDSUB). llvm-svn: 217819
* Replace dead links to "Hacker's Delight" with general references. NFC.Sanjay Patel2014-09-153-10/+10
| | | | llvm-svn: 217814
* MC: Add support for BigObjDavid Majnemer2014-09-151-59/+91
| | | | | | | | | | | | | | | | | | | | | | | | Teach WinCOFFObjectWriter how to write -mbig-obj style object files; these object files allow for more sections inside an object file. Our support for BigObj is notably different from binutils and cl: we implicitly upgrade object files to BigObj instead of asking the user to compile the same file *again* but with another flag. This matches up with how LLVM treats ELF variants. This was tested by forcing LLVM to always emit BigObj files and running the entire test suite. A specific test has also been added. I've lowered the maximum number of sections in a normal COFF file, VS "14" CTP 3 supports no more than 65279 sections. This is important otherwise we might not switch to BigObj quickly enough, leaving us with a COFF file that we couldn't link. yaml2obj support is all that remains to implement. Differential Revision: http://reviews.llvm.org/D5349 llvm-svn: 217812
* Add return that was lost somehow in my last commit.Benjamin Kramer2014-09-151-0/+1
| | | | llvm-svn: 217810
* Remove ancient hack that was emulating move semantics with reference counting.Benjamin Kramer2014-09-151-20/+13
| | | | | | No functionality change. llvm-svn: 217808
* Fix memory leak in error paths in YAMLTraits by using unique_ptrDavid Blaikie2014-09-151-31/+21
| | | | | | | | | There's some other cleanup that could happen here, but this is at least the mechanical transformation to unique_ptr. Derived from a patch by Anton Yartsev. llvm-svn: 217803
* Fix a lot of confusion around inserting nops on empty functions.Rafael Espindola2014-09-154-22/+7
| | | | | | | | | | | | | | | | On MachO, and MachO only, we cannot have a truly empty function since that breaks the linker logic for atomizing the section. When we are emitting a frame pointer, the presence of an unreachable will create a cfi instruction pointing past the last instruction. This is perfectly fine. The FDE information encodes the pc range it applies to. If some tool cannot handle this, we should explicitly say which bug we are working around and only work around it when it is actually relevant (not for ELF for example). Given the unreachable we could omit the .cfi_def_cfa_register, but then again, we could also omit the entire function prologue if we wanted to. llvm-svn: 217801
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