diff options
author | Toma Tabacu <toma.tabacu@imgtec.com> | 2014-09-16 10:19:03 +0000 |
---|---|---|
committer | Toma Tabacu <toma.tabacu@imgtec.com> | 2014-09-16 10:19:03 +0000 |
commit | 18227e6f203189fabe7c9adb518e179fc71a7d3d (patch) | |
tree | 8cc43056aec1bce8c9274a300cd7a9d6c4294169 /llvm/lib | |
parent | 25cdd222b0afbb71dc3c1caef17ff4258c49422d (diff) | |
download | bcm5719-llvm-18227e6f203189fabe7c9adb518e179fc71a7d3d.tar.gz bcm5719-llvm-18227e6f203189fabe7c9adb518e179fc71a7d3d.zip |
[mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to MipsInstrInfo.td.
Patch by Vasileios Kalintiris.
Differential Revision: http://reviews.llvm.org/D5244
llvm-svn: 217868
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 3 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 2 |
2 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 0e5c6b386d0..499253b1179 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -452,9 +452,6 @@ def : MipsInstAlias<"daddu $rs, $imm", def : MipsInstAlias<"dadd $rs, $imm", (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 0>, ISA_MIPS3_NOT_32R6_64R6; -def : MipsInstAlias<"addu $rs, $imm", - (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), - 0>; def : MipsInstAlias<"dsll $rd, $rt, $rs", (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS3; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 59cd5fa849d..138f70386e7 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1436,6 +1436,8 @@ def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>, ISA_MIPS1_NOT_32R6_64R6; def : MipsInstAlias<"addu $rs, $rt, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; +def : MipsInstAlias<"addu $rs, $imm", + (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; def : MipsInstAlias<"add $rs, $rt, $imm", (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6; |