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* [AVX512] Remove masked VPERMD/VPERMQ/VPERMILPS/VPERMILPD intrinsics. They ↵Craig Topper2016-07-041-16/+0
| | | | | | were autoupgraded to native IR in r274506 and r274506. llvm-svn: 274519
* AMDGPU/R600: Add indentation to VTX and TEX fetch asm stringsJan Vesely2016-07-041-2/+2
| | | | | | | | These are printed as part of Fetch clauses. Differential Revision: http://reviews.llvm.org/D21730 llvm-svn: 274517
* Revert "[Thumb] Reapply r272251 with a fix for PR28348"James Molloy2016-07-041-40/+1
| | | | | | This reverts commit r274510 - it made green dragon unhappy. llvm-svn: 274512
* [Thumb] Reapply r272251 with a fix for PR28348James Molloy2016-07-041-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | We were using DAG->getConstant instead of DAG->getTargetConstant. This meant that we could inadvertently increase the use count of a constant if stars aligned, which it did in this testcase. Increasing the use count of the constant could cause ISel to fall over (because DAGToDAG lowering assumed the constant had only one use!) Original commit message: [Thumb] Select a BIC instead of AND if the immediate can be encoded more optimally negated If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead; int i(int a) { return a & 0xfffffeec; } Used to produce: ldr r1, [CONSTPOOL] ands r0, r1 CONSTPOOL: 0xfffffeec And now produces: movs r1, #255 adds r1, #20 ; Less costly immediate generation bics r0, r1 llvm-svn: 274510
* [X86][AVX512] Autoupgrade the VPERMPD/VPERMQ intrinsicsSimon Pilgrim2016-07-041-0/+18
| | | | llvm-svn: 274506
* [X86][AVX512] Autoupgrade the VPERMILPD/VPERMILPS intrinsicsSimon Pilgrim2016-07-041-1/+3
| | | | llvm-svn: 274498
* Fixed warning caused by r274402.Eric Liu2016-07-041-5/+5
| | | | llvm-svn: 274497
* Add writeonly IR attributeNicolai Haehnle2016-07-049-22/+49
| | | | | | | | | | | | | | | | | Summary: This complements the earlier addition of IntrWriteMem and IntrWriteArgMem LLVM intrinsic properties, see D18291. Also start using the attribute for memset, memcpy, and memmove intrinsics, and remove their special-casing in BasicAliasAnalysis. Reviewers: reames, joker.eph Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18714 llvm-svn: 274485
* [CodeGen] Make the code that detects a if a shuffle is really a ↵Craig Topper2016-07-041-33/+41
| | | | | | | | | | concatenation of the inputs more general purpose. We can now handle concatenation of each source multiple times. The previous code just checked for each source to appear once in either order. This also now handles an entire source vector sized piece having undef indices correctly. We now concat with UNDEF instead of using one of the sources. This is responsible for the test case change. llvm-svn: 274483
* Reformat blank lines.NAKAMURA Takumi2016-07-042-11/+10
| | | | llvm-svn: 274481
* Reformat comment lines.NAKAMURA Takumi2016-07-042-9/+9
| | | | llvm-svn: 274480
* Untabify.NAKAMURA Takumi2016-07-043-6/+5
| | | | llvm-svn: 274479
* Reformat.NAKAMURA Takumi2016-07-042-32/+30
| | | | llvm-svn: 274478
* [X86] Add shuffle mask rescaling helper function. NFCI.Simon Pilgrim2016-07-031-12/+26
| | | | llvm-svn: 274476
* [X86][AVX2] Merge unary permute matching behind the same V2.isUndef() ↵Simon Pilgrim2016-07-031-9/+8
| | | | | | condition. NFCI. llvm-svn: 274474
* [X86][AVX512] Add support for 512-bit shuffle lowering to VPERMPD/VPERMQSimon Pilgrim2016-07-031-14/+39
| | | | llvm-svn: 274473
* [CodeGen] Teach OR combine of shuffles involving zero vectors to better ↵Craig Topper2016-07-031-5/+10
| | | | | | | | handle undef indices. Undef indices can now be treated as zeros. Or if its undef ORed with zero, we will keep the undef. llvm-svn: 274472
* [MBB] add a missing corner case in UpdateTerminator()Haicheng Wu2016-07-031-10/+20
| | | | | | | | | | After the block placement, if a block ends with a conditional branch, but the next block is not its successor. The conditional branch should be changed to unconditional branch. This patch fixes PR28307, PR28297, PR28402. Differential Revision: http://reviews.llvm.org/D21811 llvm-svn: 274470
* [X86][AVX512] Add support for VPERMPD/VPERMQ masked shuffle commentsSimon Pilgrim2016-07-031-0/+16
| | | | llvm-svn: 274469
* [X86][AVX512] Add support for 512-bit shuffle decoding of VPERMPD/VPERMQSimon Pilgrim2016-07-034-26/+30
| | | | llvm-svn: 274468
* [X86][AVX] Renamed VPERMILPI shuffle comment macros to be more specificSimon Pilgrim2016-07-031-27/+27
| | | | llvm-svn: 274467
* [X86][AVX512] Add support for VPALIGNR/PSHUFD/PSHUFHW/PSHUFLW masked shuffle ↵Simon Pilgrim2016-07-031-0/+16
| | | | | | comments llvm-svn: 274466
* [InstCombine] enable vector select of bools -> logic foldsSanjay Patel2016-07-031-5/+8
| | | | llvm-svn: 274465
* [X86][AVX512] Add support for UNPCK masked shuffle commentsSimon Pilgrim2016-07-031-1/+51
| | | | llvm-svn: 274464
* fix formatting; NFCSanjay Patel2016-07-031-6/+6
| | | | llvm-svn: 274463
* [X86][AVX512] Add support for VPERM/VSHUF masked shuffle commentsSimon Pilgrim2016-07-031-0/+56
| | | | llvm-svn: 274462
* [X86][AVX512] Add support for PMOVZX masked shuffle commentsSimon Pilgrim2016-07-031-0/+34
| | | | llvm-svn: 274461
* [X86][AVX512] Add support for masked shuffle commentsSimon Pilgrim2016-07-031-2/+53
| | | | | | | | | | This patch adds support for including the avx512 mask register information in the mask/maskz versions of shuffle instruction comments. This initial version just adds support for MOVDDUP/MOVSHDUP/MOVSLDUP to reduce the mass of test regenerations, other shuffle instructions can be added in due course. Differential Revision: http://reviews.llvm.org/D21953 llvm-svn: 274459
* [X86][AVX512] Add support for lowering shuffles to VPERMILPSSimon Pilgrim2016-07-031-0/+4
| | | | llvm-svn: 274458
* PR28400: Partly undo r274440 to bring test-suite back to life with the new PMSean Silva2016-07-031-1/+2
| | | | | | | | | PR28400 seems to be not an isolated issue, but a general problem related to caching analyses. We will need to discuss on llvm-dev. A test case is in the PR. llvm-svn: 274457
* [PM] Some preparatory refactoring to minimize the diff of D21921Sean Silva2016-07-031-14/+20
| | | | llvm-svn: 274456
* Remove dead TLI arg of isKnownNonNull and propagate deadness. NFC.Sean Silva2016-07-026-57/+34
| | | | | | | | | | | | | | This actually uncovered a surprisingly large chain of ultimately unused TLI args. From what I can gather, this argument is a remnant of when isKnownNonNull would look at the TLI directly. The current approach seems to be that InferFunctionAttrs runs early in the pipeline and uses TLI to annotate the TLI-dependent non-null information as return attributes. This also removes the dependence of functionattrs on TLI altogether. llvm-svn: 274455
* [PM] Port LoopAccessInfo analysis to new PMXinliang David Li2016-07-023-0/+31
| | | | | | | It is implemented as a LoopAnalysis pass as discussed and agreed upon. llvm-svn: 274452
* Fix spelling.Simon Pilgrim2016-07-021-2/+2
| | | | llvm-svn: 274451
* [X86][AVX512] Add support for lowering shuffles to VPERMILPDSimon Pilgrim2016-07-021-0/+11
| | | | llvm-svn: 274450
* [PM] Some preparatory refactoring to minimize the diff of D21921Sean Silva2016-07-021-15/+17
| | | | | | The main change here is just moving stuff to static functions. llvm-svn: 274446
* [PM] Preparatory cleanups to ArgumentPromotion.Sean Silva2016-07-021-54/+74
| | | | | | | This pulls some obvious changes out of http://reviews.llvm.org/D21921 to minimize the diff. llvm-svn: 274445
* [X86][AVX512] Add support for 512-bit PSHUFB loweringSimon Pilgrim2016-07-021-2/+7
| | | | llvm-svn: 274444
* [X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to ↵Simon Pilgrim2016-07-021-18/+0
| | | | | | generic IR llvm-svn: 274443
* [PM] Fix a small typo from when I ported JumpThreadingSean Silva2016-07-021-1/+1
| | | | llvm-svn: 274440
* [X86][AVX512] Autoupgrade the MOVDDUP/MOVSLDUP/MOVSHDUP intrinsicsSimon Pilgrim2016-07-021-0/+25
| | | | llvm-svn: 274439
* [DIBuilder] Remove dead code. NFC.Benjamin Kramer2016-07-021-34/+0
| | | | llvm-svn: 274438
* [Hexagon] Create global std::map lazily.Benjamin Kramer2016-07-021-3/+3
| | | | | | | | This could of course be a simple binary search with no global state involved at all if someone cares enough. Just don't make everyone linking the hexagon backend pay for it on process startup and shutdown. llvm-svn: 274437
* [X86][AVX512] Add support for lowering shuffles to MOVDDUP/MOVSLDUP/MOVSHDUPSimon Pilgrim2016-07-021-0/+19
| | | | llvm-svn: 274436
* Use arrays or initializer lists to feed ArrayRefs instead of SmallVector ↵Benjamin Kramer2016-07-029-55/+28
| | | | | | | | where possible. No functionality change intended. llvm-svn: 274431
* [esan|cfrag] Add counters for struct array accessesQin Zhao2016-07-021-34/+87
| | | | | | | | | | | | | | | | | Summary: Adds one counter to the struct counter array for counting struct array accesses. Adds instrumentation to insert counter update for struct array accesses. Reviewers: aizatsky Subscribers: llvm-commits, bruening, eugenis, kcc, zhaoqin, vitalybuka Differential Revision: http://reviews.llvm.org/D21594 llvm-svn: 274420
* [SystemZ] Move misplaced SystemZ::TDC to non-memory opcode range.Marcin Koscielnicki2016-07-022-7/+7
| | | | llvm-svn: 274417
* Add RenderScript ArchTypePirama Arumuga Nainar2016-07-021-73/+91
| | | | | | | | | | | | | | | | Summary: Add renderscript32 and renderscript64 ArchTypes. This is to configure the ABI requirement on 32-bit RenderScript that 'long' types have 64-bit size and alignment. 64-bit RenderScript is the same as AArch64, but is added here for completeness. Reviewers: echristo, rsmith Subscribers: aemerson, jfb, rampitec, dschuff, mehdi_amini, llvm-commits, srhines Differential Revision: http://reviews.llvm.org/D21333 llvm-svn: 274412
* [PM] Port ConstantHoisting to the new Pass ManagerMichael Kuperstein2016-07-024-135/+56
| | | | | | Differential Revision: http://reviews.llvm.org/D21945 llvm-svn: 274411
* [codeview] Set the Nested and Scoped ClassOptions based on the scope chainReid Kleckner2016-07-021-12/+31
| | | | | | These are set on both the declaration record and the definition record. llvm-svn: 274410
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