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* [ARM] GlobalISel: Fixup r307365Diana Picus2017-07-071-11/+10
| | | | | | | Rename member DebugLoc -> DbgLoc (so it doesn't conflict with the class name). llvm-svn: 307366
* [ARM] GlobalISel: Select hard G_FCMP for s32Diana Picus2017-07-071-63/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We lower to a sequence consisting of: - MOVi 0 into a register - VCMPS to do the actual comparison and set the VFP flags - FMSTAT to move the flags out of the VFP unit - MOVCCi to either use the "zero register" that we have previously set with the MOVi, or move 1 into the result register, based on the values of the flags As was the case with soft-float, for some predicates (one, ueq) we actually need two comparisons instead of just one. When that happens, we generate two VCMPS-FMSTAT-MOVCCi sequences and chain them by means of using the result of the first MOVCCi as the "zero register" for the second one. This is a bit overkill, since one comparison followed by two non-flag-setting conditional moves should be enough. In any case, the backend manages to CSE one of the comparisons away so it doesn't matter much. Note that unlike SelectionDAG and FastISel, we always use VCMPS, and not VCMPES. This makes the code a lot simpler, and it also seems correct since the LLVM Lang Ref defines simple true/false returns if the operands are QNaN's. For SNaN's, even VCMPS throws an Invalid Operand exception, so they won't be slipping through unnoticed. Implementation-wise, this introduces a template so we can share the same code that we use for handling integer comparisons, since the only differences are in the details (exact opcodes to be used etc). Hopefully this will be easy to extend to s64 G_FCMP. llvm-svn: 307365
* Reduce code duplication.Rafael Espindola2017-07-071-33/+27
| | | | | | | By addding a mapNameToDWARFSection we only need to check section names in one place. llvm-svn: 307359
* [PDB] Teach libpdb to write DBI Stream ECNames.Zachary Turner2017-07-073-3/+19
| | | | | | | | | | | | | | | | | | | | | | | Based strictly on the name, this seems to have something to do width edit & continue. The goal of this patch has nothing to do with supporting edit and continue though. msvc link.exe writes very basic information into this area even when *not* compiling with support for E&C, and so the goal here is to bring lld-link to parity. Since we cannot know what assumptions standard tools make about the content of PDB files, we need to be as close as possible. This ECNames data structure is a standard PDB string hash table. link.exe puts a single string into this hash table, which is the full path to the PDB file on disk. It then references this string from the module descriptor for the compiler generated `* Linker *` module. With this patch, lld-link will generate the exact same sequence of bytes as MSVC link for this subsection for a given object file input (as reported by `llvm-pdbutil bytes -ec`). llvm-svn: 307356
* RegisterScavenging: Fix PR33687Matthias Braun2017-07-071-2/+9
| | | | | | | | | When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
* LiveRegUnits: Rename accumulateBackward()->accumulate()Matthias Braun2017-07-073-3/+3
| | | | | | | | | Contrary to the stepForward()/stepBackward() method accumulate() doesn't have a direction as defs, uses and clobbers all have the same effect. Also improve the documentation comment. llvm-svn: 307351
* [ORC] Errorize the ORC APIs.Lang Hames2017-07-078-61/+158
| | | | | | | | This patch updates the ORC layers and utilities to return and propagate llvm::Errors where appropriate. This is necessary to allow ORC to safely handle error cases in cross-process and remote JITing. llvm-svn: 307350
* [InferAddressSpaces] Fix assertion about null pointerYaxun Liu2017-07-071-1/+2
| | | | | | | | | | | | | InferAddressSpaces does not check address space in collectFlatAddressExpressions, which causes values with non flat address space put into Postorder and causes assertion in cloneValueWithNewAddressSpace. This patch fixes assertion in OpenCL 2.0 conformance test generic_address_space subtest for amdgcn target. Differential Revision: https://reviews.llvm.org/D34991 llvm-svn: 307349
* [WebAssembly] Support weak defined symbolsSam Clegg2017-07-072-75/+88
| | | | | | | | | | | | Model weakly defined symbols as symbols that are both exports and imported and marked as weak. Local references to the symbols refer to the import but the linker can resolve this to the weak export if not strong symbol is found at link time. Differential Revision: https://reviews.llvm.org/D35029 llvm-svn: 307348
* Extend memcpy expansion in Transform/Utils to handle wider operand types.Sean Fertile2017-07-074-21/+340
| | | | | | | | | | | Adds loop expansions for known-size and unknown-sized memcpy calls, allowing the target to provide the operand types through TTI callbacks. The default values for the TTI callbacks use int8 operand types and matches the existing behaviour if they aren't overridden by the target. Differential revision: https://reviews.llvm.org/D32536 llvm-svn: 307346
* Revert r307342, r307343.Evgeniy Stepanov2017-07-071-37/+0
| | | | | | | | | | Revert "Copy arguments passed by value into explicit allocas for ASan." Revert "[asan] Add end-to-end tests for overflows of byval arguments." Build failure on lldb-x86_64-ubuntu-14.04-buildserver. Test failure on clang-cmake-aarch64-42vma and sanitizer-x86_64-linux-android. llvm-svn: 307345
* Copy arguments passed by value into explicit allocas for ASan.Evgeniy Stepanov2017-07-071-0/+37
| | | | | | | | | | | | | | ASan determines the stack layout from alloca instructions. Since arguments marked as "byval" do not have an explicit alloca instruction, ASan does not produce red zones for them. This commit produces an explicit alloca instruction and copies the byval argument into the allocated memory so that red zones are produced. Patch by Matt Morehouse. Differential revision: https://reviews.llvm.org/D34789 llvm-svn: 307342
* [SafepointIRVerifier] NFC: Refactor code for identifying exclusive base typeAnna Thomas2017-07-071-37/+72
| | | | | | | | | Added a new Enum to identify if the base pointer is exclusively null or exlusively some constant or not exclusively any constant. Converted the base pointer identification method from recursive to iterative form. llvm-svn: 307340
* [ConstHoisting] Turn on consthoist-with-block-frequency by default.Wei Mi2017-07-071-1/+1
| | | | | | | | | | | Using profile information to guide consthoisting is generally helpful for performance, so the patch turns it on by default. No compile time or perf regression were found using spec2000 and spec2006 on x86. Some significant improvement (>20%) was seen on internal benchmarks. Differential Revision: https://reviews.llvm.org/D35063 llvm-svn: 307338
* Reverting r307326 because it breaks clang tests.Michael Kuperstein2017-07-063-32/+11
| | | | llvm-svn: 307334
* [InstCombine] No need to pass DataLayout to helper functions if we're ↵Craig Topper2017-07-061-7/+5
| | | | | | passing the InstCombiner object. We can just ask it for the DataLayout. NFC llvm-svn: 307333
* [InstCombine] Remove unused arguments from some helper functions. NFCCraig Topper2017-07-061-7/+5
| | | | llvm-svn: 307332
* [InstCombine] Change a couple helper functions to only take the IRBuilder as ↵Craig Topper2017-07-061-9/+10
| | | | | | an argument and not the whole InstCombiner object. NFC llvm-svn: 307331
* [ConstHoisting] choose to hoist when frequency is the same.Wei Mi2017-07-061-2/+11
| | | | | | | | | | | | The patch is to adjust the strategy of frequency based consthoisting: Previously when the candidate block has the same frequency with the existing blocks containing a const, it will not hoist the const to the candidate block. For that case, now we change the strategy to hoist the const if only existing blocks have more than one block member. This is helpful for reducing code size. Differential Revision: https://reviews.llvm.org/D35084 llvm-svn: 307328
* [NVPTX] Add lowering of i128 params.Michael Kuperstein2017-07-063-11/+32
| | | | | | | | | | | | | | | | | The patch adds support of i128 params lowering. The changes are quite trivial to support i128 as a "special case" of integer type. With this patch, we lower i128 params the same way as aggregates of size 16 bytes: .param .b8 _ [16]. Currently, NVPTX can't deal with the 128 bit integers: * in some cases because of failed assertions like ValVTs.size() == OutVals.size() && "Bad return value decomposition" * in other cases emitting PTX with .i128 or .u128 types (which are not valid [1]) [1] http://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fundamental-types Differential Revision: https://reviews.llvm.org/D34555 Patch by: Denys Zariaiev (denys.zariaiev@gmail.com) llvm-svn: 307326
* [COFF, AArch64] Set the private label prefix to .LMartin Storsjo2017-07-061-0/+2
| | | | | | | | | | This fixes calls to external functions starting with a capital L, fixing errors like this: fatal error: error in backend: assembler label 'LocalFree' can not be undefined Differential Revision: https://reviews.llvm.org/D35079 llvm-svn: 307317
* AMDGPU: Add macro fusion schedule DAG mutationMatt Arsenault2017-07-064-0/+86
| | | | | | Try to increase opportunities to shrink vcc uses. llvm-svn: 307313
* AMDGPU: Minor cleanup of shrinking logicMatt Arsenault2017-07-061-8/+4
| | | | llvm-svn: 307312
* [AMDGPU] Always use rcp + mul with fast mathStanislav Mekhanoshin2017-07-062-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Regardless of relaxation options such as -cl-fast-relaxed-math we are producing rather long code for fdiv via amdgcn_fdiv_fast intrinsic. This intrinsic is used to replace fdiv with 2.5ulp metadata and does not handle denormals, thus believed to be fast. An fdiv instruction can also have fast math flag either by itself or together with fpmath metadata. Clang used with a relaxation flag always produces both metadata and fast flag: %div = fdiv fast float %v, %0, !fpmath !12 !12 = !{float 2.500000e+00} Current implementation ignores fast flag and favors metadata. An instruction with just fast flag would be lowered to a fastest rcp + mul, but that never happen on practice because of described mutual clang and BE behavior. This change allows an "fdiv fast" to be always lowered as rcp + mul. Differential Revision: https://reviews.llvm.org/D34844 llvm-svn: 307308
* [lib/LTO] Add a comment to explain where we set the linkage in the summary.Davide Italiano2017-07-061-0/+5
| | | | | | Pointed out by Teresa! llvm-svn: 307305
* [ValueTracking] Support icmps fed by 'and' and 'or'.Chad Rosier2017-07-061-7/+32
| | | | | | | | | | This patch adds support for handling some forms of ands and ors in ValueTracking's isImpliedCondition API. PR33611 https://reviews.llvm.org/D34901 llvm-svn: 307304
* [LTO] Fix the interaction between linker redefined symbols and ThinLTODavide Italiano2017-07-062-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | This is the same as r304719 but for ThinLTO. The substantial difference is that in this case we don't have whole visibility, just the summary. In the LTO case, when we got the resolution for the input file we could just see if the linker told us whether a symbol was linker redefined (using --wrap or --defsym) and switch the linkage directly for the GV. Here, we have the summary. So, we record that the linkage changed from <whatever it was> to $weakany to prevent IPOs across this symbol boundaries and actually just switch the linkage at FunctionImport time. This patch should also fixes the lld bits (as all the scaffolding for communicating if a symbol is linker redefined should be there & should be the same), but I'll make sure to add some tests there as well. Fixes PR33192. Differential Revision: https://reviews.llvm.org/D35064 llvm-svn: 307303
* [GISel]: Enhance the MachineIRBuilder APIAditya Nandakumar2017-07-061-3/+2
| | | | | | | | | | | | | | | | | | | | Allows the MachineIRBuilder APIs to directly create registers (based on LLT or TargetRegisterClass) as well as accept MachineInstrBuilders and implicitly converts to register(with getOperand(0).getReg()). Eg usage: LLT s32 = LLT::scalar(32); auto C32 = Builder.buildConstant(s32, 32); auto Tmp = Builder.buildInstr(TargetOpcode::G_SUB, s32, C32, OtherReg); auto Tmp2 = Builder.buildInstr(Opcode, DstReg, Builder.buildConstant(s32, 31)); .... Only a few methods added for now. Reviewed by Tim llvm-svn: 307302
* Prototype: Reduce llvm-profdata merge memory usage furtherDavid Blaikie2017-07-062-20/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The InstrProfWriter already stores the name and hash of the record in the nested maps it uses for lookup while merging - this data is duplicated in the value within the maps. Refactor the InstrProfRecord to use a nested struct for the counters themselves so that InstrProfWriter can use this nested struct alone without the name or hash duplicated there. This work is incomplete, but enough to demonstrate the value (around a 50% decrease in memory usage for a large test case (10GB -> 5GB)). Though most of that decrease is probably from removing the SoftInstrProfError as well, but I haven't implemented a replacement for it yet. (it needs to go with the counters, because the operations on the counters - merging, etc, are where the failures are - unlike the name/hash which are totally unused by those counter-related operations and thus easy to split out) Ongoing discussion about removing SoftInstrProfError as a field of the InstrProfRecord is happening on the thread that added it - including the possibility of moving back towards an earlier version of that proposed patch that passed SoftInstrProfError through the various APIs, rather than as a member of InstrProfRecord. Reviewers: davidxl Differential Revision: https://reviews.llvm.org/D34838 llvm-svn: 307298
* [InstCombine] Remove include of DIBuilder.h and Dwarf.h as they don't appear ↵Craig Topper2017-07-061-2/+0
| | | | | | to be necessary. llvm-svn: 307295
* Modify constraints in `llvm::canReplaceOperandWithVariable`Leo Li2017-07-061-2/+8
| | | | | | | | | | | | | | | | | Summary: `Instruction::Switch`: only first operand can be set to a non-constant value. `Instruction::InsertValue` both the first and the second operand can be set to a non-constant value. `Instruction::Alloca` return true for non-static allocation. Reviewers: efriedma Reviewed By: efriedma Subscribers: srhines, pirama, llvm-commits Differential Revision: https://reviews.llvm.org/D34905 llvm-svn: 307294
* [Constants] Replace calls to ConstantInt::equalsInt(0)/equalsInt(1) with ↵Craig Topper2017-07-064-17/+17
| | | | | | isZero and isOne. NFCI llvm-svn: 307293
* [Constants] If we already have a ConstantInt*, prefer to use ↵Craig Topper2017-07-0625-45/+45
| | | | | | | | isZero/isOne/isMinusOne instead of isNullValue/isOneValue/isAllOnesValue inherited from Constant. NFCI Going through the Constant methods requires redetermining that the Constant is a ConstantInt and then calling isZero/isOne/isMinusOne. llvm-svn: 307292
* [LoopUnrollRuntime] Bailout when multiple exiting blocks to the unique latch ↵Anna Thomas2017-07-061-4/+5
| | | | | | | | | | | | | | exit block Currently, we do not support multiple exiting blocks to the latch exit block. However, this bailout wasn't triggered when we had a unique exit block (which is the latch exit), with multiple exiting blocks to that unique exit. Moved the bailout so that it's triggered in both cases and added testcase. llvm-svn: 307291
* [InstCombine] Remove Builder argument from InstCombiner::tryFactorization. NFCCraig Topper2017-07-062-8/+6
| | | | | | Builder is already a member of the InstCombiner class so we can use it with passing it. llvm-svn: 307290
* Fix spelling in comments. NFCI.Simon Pilgrim2017-07-061-3/+3
| | | | llvm-svn: 307288
* Bitcode: Include any strings added to the string table in the module hash.Peter Collingbourne2017-07-061-6/+15
| | | | | | Differential Revision: https://reviews.llvm.org/D35037 llvm-svn: 307286
* [SimplifyCFG] Move a portion of an if statement that should already be ↵Craig Topper2017-07-061-2/+2
| | | | | | | | | | | | | | | | implied to an assert Summary: In this code we got to Dom by following the predecessor link of BB. So it stands to reason that BB should also show up as a successor of Dom's terminator right? There isn't a way to have the CFG connect in only one direction is there? Reviewers: jmolloy, davide, mcrosier Reviewed By: mcrosier Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D35025 llvm-svn: 307276
* [InstCombine] Change helper method to a file local static method. NFCCraig Topper2017-07-062-5/+5
| | | | llvm-svn: 307275
* [InstCombine] Clarify comment to mention other transform that it does. NFCCraig Topper2017-07-061-1/+2
| | | | llvm-svn: 307274
* [InstCombine] Add single use checks to SimplifyBSwap to ensure we are really ↵Craig Topper2017-07-061-4/+9
| | | | | | | | | | | | saving instructions Bswap isn't a simple operation so we need to make sure we are really removing a call to it before doing these simplifications. For the case when both LHS and RHS are bswaps I've allowed it to be moved if either LHS or RHS has a single use since that at least allows us to move it later where it might find another bswap to combine with and it decreases the use count on the other side so maybe the other user can be optimized. Differential Revision: https://reviews.llvm.org/D34974 llvm-svn: 307273
* [InstCombine] Don't create extra ConstantInt objects in foldSelectICmpAnd. NFCICraig Topper2017-07-061-19/+17
| | | | | | Instead just use APInt objects and only create a ConstantInt at the end if we need it for the Offset. llvm-svn: 307270
* [LSR] Narrow search space by filtering non-optimal formulae with the same ↵Wei Mi2017-07-061-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ScaledReg and Scale. When the formulae search space is huge, LSR uses a series of heuristic to keep pruning the search space until the number of possible solutions are within certain limit. The big hammer of the series of heuristics is NarrowSearchSpaceByPickingWinnerRegs, which picks the register which is used by the most LSRUses and deletes the other formulae which don't use the register. This is a effective way to prune the search space, but quite often not a good way to keep the best solution. We saw cases before that the heuristic pruned the best formula candidate out of search space. To relieve the problem, we introduce a new heuristic called NarrowSearchSpaceByFilterFormulaWithSameScaledReg. The basic idea is in order to reduce the search space while keeping the best formula, we want to keep as many formulae with different Scale and ScaledReg as possible. That is because the central idea of LSR is to choose a group of loop induction variables and use those induction variables to represent LSRUses. An induction variable candidate is often represented by the Scale and ScaledReg in a formula. If we have more formulae with different ScaledReg and Scale to choose, we have better opportunity to find the best solution. That is why we believe pruning search space by only keeping the best formula with the same Scale and ScaledReg should be more effective than PickingWinnerReg. And we use two criteria to choose the best formula with the same Scale and ScaledReg. The first criteria is to select the formula using less non shared registers, and the second criteria is to select the formula with less cost got from RateFormula. The patch implements the heuristic before NarrowSearchSpaceByPickingWinnerRegs, which is the last resort. Testing shows we get 1.8% and 2% on two internal benchmarks on x86. llvm nightly testsuite performance is neutral. We also tried lsr-exp-narrow and it didn't help on the two improved internal cases we saw. Differential Revision: https://reviews.llvm.org/D34583 llvm-svn: 307269
* [X86][SSE4A] Add support for shuffle combining to INSERTQI.Simon Pilgrim2017-07-061-0/+16
| | | | llvm-svn: 307268
* Doxygen formatting. NFCIJoel Jones2017-07-061-2/+12
| | | | llvm-svn: 307263
* [MachineVerifier] Add check that tied physregs aren't different.Mikael Holmen2017-07-061-0/+8
| | | | | | | | | | | | | | | | Summary: Added MachineVerifier code to check register ties more thoroughly, especially so that physical registers that are tied are the same. This may help e.g. when creating MIR files. Original patch by Jesper Antonsson Reviewers: stoklund, sanjoy, qcolombet Reviewed By: qcolombet Subscribers: qcolombet, llvm-commits Differential Revision: https://reviews.llvm.org/D34394 llvm-svn: 307259
* [X86][SSE] combineX86ShuffleChain - merge duplicate creations of integer ↵Simon Pilgrim2017-07-061-20/+12
| | | | | | mask types llvm-svn: 307257
* [X86][SSE] combineX86ShuffleChain - merge duplicate 'Zeroable' element masksSimon Pilgrim2017-07-061-20/+12
| | | | llvm-svn: 307255
* [X86][SSE4A] Add support for shuffle combining to EXTRQ.Simon Pilgrim2017-07-061-1/+28
| | | | llvm-svn: 307254
* [X86][SSE4A] Split EXTRQ/INSERTQ shuffle matching from lowering. NFCI.Simon Pilgrim2017-07-061-99/+112
| | | | | | First step toward supporting shuffle combining to EXTRQ/INSERTQ. llvm-svn: 307250
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