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* Improve compile-time performance in computeKnownBitsFromAssume.Sander de Smalen2019-04-101-217/+214
| | | | | | | | | | | | | | This patch changes the order of pattern matching by first testing a compare instruction's predicate, before doing the pattern match for the whole expression tree. Patch by Paul Walker. Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D60504 llvm-svn: 358097
* [X86][AVX] getTargetConstantBitsFromNode - extract bits from ↵Simon Pilgrim2019-04-101-0/+13
| | | | | | X86ISD::SUBV_BROADCAST llvm-svn: 358096
* [InstCombine] Handle saddo always overflowNikita Popov2019-04-101-3/+3
| | | | | | | | | Followup to D60483: Handle AlwaysOverflow conditions for saddo as well. Differential Revision: https://reviews.llvm.org/D60497 llvm-svn: 358095
* [MachineOutliner] Replace ostringstream based string concatenation with TwineFangrui Song2019-04-101-10/+4
| | | | | | | | This makes my libLLVMCodeGen.so.9svn 4936 bytes smaller. While here, delete unused #include <map> llvm-svn: 358089
* [LLVM-C] Correct The Current Debug Location Accessors (Again)Robert Widmann2019-04-102-1/+15
| | | | | | | | | | | | | | Summary: Resubmitting D60484 with the conflicting Go bindings renamed to avoid collisions. Reviewers: whitequark, deadalnix Subscribers: hiraditya, llvm-commits, sammccall Tags: #llvm Differential Revision: https://reviews.llvm.org/D60511 llvm-svn: 358086
* [AArch64] Add lowering pattern for scalar fp16 facge and facgtDiogo N. Sampaio2019-04-101-0/+10
| | | | | | | | | | | | | | | | Summary: The fp16 scalar version of facge and facgt requires a custom patter matching, as the result type is not the same width of the operands. Reviewers: olista01, javed.absar, pbarrio Reviewed By: javed.absar Subscribers: kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60212 llvm-svn: 358083
* Revert "[LLVM-C] Correct The Current Debug Location Accessors"Sam McCall2019-04-101-11/+1
| | | | | | | This reverts commit r358039, which added symbols that conflict with the Go bindings. llvm-svn: 358082
* [ARM] [FIX] Add missing f16 vector operations loweringDiogo N. Sampaio2019-04-102-1/+6
| | | | | | | | | | | | | | | | | | | | Summary: Add missing <8xhalf> shufflevectors pattern, when using concat_vector dag node. As well, allows <8xhalf> and <4xhalf> vldup1 operations. These instructions are required for v8.2a fp16 lowering of vmul_n_f16, vmulq_n_f16 and vmulq_lane_f16 intrinsics. Reviewers: olista01, pbarrio, LukeGeeson, efriedma Reviewed By: efriedma Subscribers: efriedma, javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60319 llvm-svn: 358081
* [NFC] Fix unused variable warning.Clement Courbet2019-04-101-3/+0
| | | | llvm-svn: 358080
* [DebugInfo] Track multiple registers in DbgEntityHistoryCalculatorDavid Stenberg2019-04-101-28/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When calculating the debug value history, DbgEntityHistoryCalculator would only keep track of register clobbering for the latest debug value per inlined entity. This meant that preceding register-described debug value fragments would live on until the next overlapping debug value, ignoring any potential clobbering. This patch amends DbgEntityHistoryCalculator so that it keeps track of all registers that a inlined entity's currently live debug values are described by. The DebugInfo/COFF/pieces.ll test case has had to be changed since previously a register-described fragment would incorrectly outlive its basic block. The parent patch D59941 is expected to increase the coverage slightly, as it makes sure that location list entries are inserted after clobbered fragments, and this patch is expected to decrease it, as it stops preceding register-described from living longer than they should. All in all, this patch and the preceding patch has a negligible effect on the output from `llvm-dwarfdump -statistics' for a clang-3.4 binary built using the RelWithDebInfo build profile. "Scope bytes covered" increases by 0.5%, and "variables with location" increases from 2212083 to 2212088, but it should improve the accuracy quite a bit. This fixes PR40283. Reviewers: aprantl, probinson, dblaikie, rnk, bjope Reviewed By: aprantl Subscribers: llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D59942 llvm-svn: 358073
* [DebugInfo] Improve handling of clobbered fragmentsDavid Stenberg2019-04-104-106/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently the DbgValueHistorymap only keeps track of clobbered registers for the last debug value that it has encountered. This could lead to preceding register-described debug values living on longer in the location lists than they should. See PR40283 for an example. This patch does not introduce tracking of multiple registers, but changes the DbgValueHistoryMap structure to allow for that in a follow-up patch. This patch is not NFC, as it at least fixes two bugs in DwarfDebug (both are covered in the new clobbered-fragments.mir test): * If a debug value was clobbered (its End pointer set), the value would still be added to OpenRanges, meaning that the succeeding location list entries could potentially contain stale values. * If a debug value was clobbered, and there were non-overlapping fragments that were still live after the clobbering, DwarfDebug would not create a location list entry starting directly after the clobbering instruction. This meant that the location list could have a gap until the next debug value for the variable was encountered. Before this patch, the history map was represented by <Begin, End> pairs, where a new pair was created for each new debug value. When dealing with partially overlapping register-described debug values, such as in the following example: DBG_VALUE $reg2, $noreg, !1, !DIExpression(DW_OP_LLVM_fragment, 32, 32) [...] DBG_VALUE $reg3, $noreg, !1, !DIExpression(DW_OP_LLVM_fragment, 64, 32) [...] $reg2 = insn1 [...] $reg3 = insn2 the history map would then contain the entries `[<DV1, insn1>, [<DV2, insn2>]`. This would leave it up to the users of the map to be aware of the relative order of the instructions, which e.g. could make DwarfDebug::buildLocationList() needlessly complex. Instead, this patch makes the history map structure monotonically increasing by dropping the End pointer, and replacing that with explicit clobbering entries in the vector. Each debug value has an "end index", which if set, points to the entry in the vector that ends the debug value. The ending entry can either be an overlapping debug value, or an instruction which clobbers the register that the debug value is described by. The ending entry's instruction can thus either be excluded or included in the debug value's range. If the end index is not set, the debug value that the entry introduces is valid until the end of the function. Changes to test cases: * DebugInfo/X86/pieces-3.ll: The range of the first DBG_VALUE, which describes that the fragment (0, 64) is located in RDI, was incorrectly ended by the clobbering of RAX, which the second (non-overlapping) DBG_VALUE was described by. With this patch we get a second entry that only describes RDI after that clobbering. * DebugInfo/ARM/partial-subreg.ll: This test seems to indiciate a bug in LiveDebugValues that is caused by it not being aware of fragments. I have added some comments in the test case about that. Also, before this patch DwarfDebug would incorrectly include a register-described debug value from a preceding block in a location list entry. Reviewers: aprantl, probinson, dblaikie, rnk, bjope Reviewed By: aprantl Subscribers: javed.absar, kristof.beyls, jdoerfert, llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D59941 llvm-svn: 358072
* [AsmPrinter] Delete unused RangeSpanList::addRangeFangrui Song2019-04-101-1/+0
| | | | llvm-svn: 358068
* MCSymbolicELF: simplify. (Flags & (x << s)) >> s is equivalent to Flags >> s & xFangrui Song2019-04-101-6/+4
| | | | llvm-svn: 358067
* MCDwarf: use write_zeroes for MCDwarfLineAddr::FixedEncodeFangrui Song2019-04-101-3/+1
| | | | | | This is more efficient than allocating a std::vector<uint8_t>. llvm-svn: 358066
* Fixup r358063Diana Picus2019-04-101-2/+2
| | | | | | Fix warning/error about mixed signedness. llvm-svn: 358065
* [ARM GlobalISel] Add some asserts. NFC.Diana Picus2019-04-101-0/+2
| | | | | | Make sure some arm opcodes don't unintentionally sneak into thumb mode. llvm-svn: 358064
* [ARM GlobalISel] Select G_FCONSTANT for VFP3Diana Picus2019-04-102-10/+59
| | | | | | | | | | | | | | | | Make it possible to TableGen code for FCONSTS and FCONSTD. We need to make two changes to the TableGen descriptions of vfp_f32imm and vfp_f64imm respectively: * add GISelPredicateCode to check that the immediate fits in 8 bits; * extract the SDNodeXForms into separate definitions and create a GISDNodeXFormEquiv and a custom renderer function for each of them. There's a lot of boilerplate to get the actual value of the immediate, but it basically just boils down to calling ARM_AM::getFP32Imm or ARM_AM::getFP64Imm. llvm-svn: 358063
* [ARM GlobalISel] Select G_FCONSTANT into poolsDiana Picus2019-04-101-0/+21
| | | | | | | Put all floating point constants into constant pools and load their values from there. llvm-svn: 358062
* [ARM GlobalISel] Map G_FCONSTANTDiana Picus2019-04-101-0/+8
| | | | llvm-svn: 358061
* [DebugInfo] Rename DbgValueHistoryMap::{InstrRange -> Entry}, NFCDavid Stenberg2019-04-106-63/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In an upcoming commit the history map will be changed so that it contains explicit entries for instructions that clobber preceding debug values, rather than Begin- End range pairs, so generalize the name to "Entry". Also, prefix the iterator variable names in buildLocationList() with "E". In an upcoming commit the entry will have query functions such as "isD(e)b(u)gValue", which could at a glance make one confuse it for iterations over MachineInstrs, so make the iterator names a bit more distinct to avoid that. Reviewers: aprantl Reviewed By: aprantl Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59939 llvm-svn: 358060
* [DebugInfo] Make InstrRange into a class, NFCDavid Stenberg2019-04-104-35/+41
| | | | | | | | | | | | | | | | | | | | Summary: Replace use of std::pair by creating a class for the debug value instruction ranges instead. This is a preparatory refactoring for improving handling of clobbered fragments. In an upcoming commit the Begin pointer will become a PointerIntPair, so it will be cleaner to have a getter for that. Reviewers: aprantl Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59938 llvm-svn: 358059
* [ScheduleDAG] Add statistics for maintaining the topological order.Florian Hahn2019-04-101-0/+8
| | | | | | | | | | | | | This is helpful to measure the impact of D60125 on maintaining topological orders. Reviewers: MatzeB, atrick, efriedma, niravd Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D60187 llvm-svn: 358058
* [VPLAN] Minor improvement to testing and debug messages.Florian Hahn2019-04-101-7/+10
| | | | | | | | | | | | 1. Use computed VF for stress testing. 2. If the computed VF does not produce vector code (VF smaller than 2), force VF to be 4. 3. Test vectorization of i64 data on AArch64 to make sure we generate VF != 4 (on X86 that was already tested on AVX). Patch by Francesco Petrogalli <francesco.petrogalli@arm.com> Differential Revision: https://reviews.llvm.org/D59952 llvm-svn: 358056
* [DWARF] Simplify LineTable::findRowInSeqFangrui Song2019-04-101-35/+11
| | | | | | | | | | | | | | We want the last row whose address is less than or equal to Address. This can be computed as upper_bound - 1, which is simpler than lower_bound followed by skipping equal rows in a loop. Since FirstRow (LowPC) does not satisfy the predicate (OrderByAddress) while LastRow-1 (HighPC) satisfies the predicate. We can decrease the search range by two, i.e. upper_bound [FirstRow,LastRow) = upper_bound [FirstRow+1,LastRow-1) llvm-svn: 358053
* [InstCombine] Handle usubo always overflowNikita Popov2019-04-101-0/+3
| | | | | | | | | | | Check AlwaysOverflow condition for usubo. The implementation is the same as the existing handling for uaddo and umulo. Handling for saddo and ssubo will follow (smulo doesn't have the necessary ValueTracking support). Differential Revision: https://reviews.llvm.org/D60483 llvm-svn: 358052
* [InstCombine] Directly call computeOverflow methods in ↵Nikita Popov2019-04-101-6/+13
| | | | | | | | | OptimizeOverflowCheck; NFC Instead of using the willOverflow helpers. This makes it easier to extend handling of AlwaysOverflows. llvm-svn: 358051
* [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y).Chen Zheng2019-04-101-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D60395 llvm-svn: 358050
* [ObjC][ARC] Convert the retainRV marker that is passed as a namedAkira Hatanaka2019-04-102-15/+8
| | | | | | | | | | | | | | | metadata into a module flag in the auto-upgrader and make the ARC contract pass read the marker as a module flag. This is needed to fix a bug where ARC contract wasn't inserting the retainRV marker when LTO was enabled, which caused objects returned from a function to be auto-released. rdar://problem/49464214 Differential Revision: https://reviews.llvm.org/D60303 llvm-svn: 358047
* [X86] Move the 2 byte VEX optimization for MOV instructions back to the ↵Craig Topper2019-04-103-54/+63
| | | | | | | | X86AsmParser::processInstruction where it used to be. Block when {vex3} prefix is present. Years ago I moved this to an InstAlias using VR128H/VR128L. But now that we support {vex3} pseudo prefix, we need to block the optimization when it is set to match gas behavior. llvm-svn: 358046
* [llvm-objdump] Don't print trailing space in dumpBytesFangrui Song2019-04-101-1/+5
| | | | | | | In disassembly output, dumpBytes prints a space, followed by a tab printed by printInstr. Remove the extra space. llvm-svn: 358045
* [Sparc] Fix incorrect MI insertion position for spilling f128.Jim Lin2019-04-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset should be inserted before new created MI for storing even register into memory. So the insertion position should be *StMI instead of II. before fixed: std %f0, [%g1+80] sethi 4, %g1 <<< add %g1, %sp, %g1 <<< this two instructions should be put before "std %f0, [%g1+80]". sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] after fixed: sethi 4, %g1 add %g1, %sp, %g1 std %f0, [%g1+80] sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] Reviewers: venkatra, jyknight Reviewed By: jyknight Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60397 llvm-svn: 358042
* [X86] Support the EVEX versions vcvt(t)ss2si and vcvt(t)sd2si with the ↵Craig Topper2019-04-102-32/+27
| | | | | | | | | | | | {evex} pseudo prefix in the assembler. The EVEX versions are ambiguous with the VEX versions based on operands alone so we had explicitly dropped them from the AsmMatcher table. Unfortunately, when we add them they incorrectly show in the table before their VEX counterparts. This is different how the prioritization normally works. To fix this we have to explicitly reject the instructions unless the {evex} prefix has been seen. llvm-svn: 358041
* [X86] Add VEX_LIG to scalar VEX/EVEX instructions that were missing it.Craig Topper2019-04-092-39/+40
| | | | | | | | | | Scalar VEX/EVEX instructions don't use the L bit and don't look at it for decoding either. So we should ignore it in our disassembler. The missing instructions here were found by grepping the raw tablegen class definitions in the tablegen debug output. llvm-svn: 358040
* [LLVM-C] Correct The Current Debug Location AccessorsRobert Widmann2019-04-091-1/+11
| | | | | | | | | | | | | | | | Summary: Deprecate the existing accessors for the "current debug location" of an IRBuilder. The setter could not handle being reset to NULL, and the getter would create bogus metadata if the NULL location was returned. Provide direct metadata-based accessors instead. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60484 llvm-svn: 358039
* [LLVM-C] Add Bindings to Access an Instruction's DebugLocRobert Widmann2019-04-091-0/+11
| | | | | | | | | | | | | | | | Summary: Provide direct accessors to supplement LLVMSetInstDebugLocation. In addition, properly accept and return the NULL location. The old accessors provided no way to do this, so the current debug location cannot currently be cleared. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60481 llvm-svn: 358038
* [LLVM-C] Add Section and Symbol Iterator Accessors for Object File BinariesRobert Widmann2019-04-091-0/+28
| | | | | | | | | | | | | | | | Summary: This brings us to full feature parity with the old API, so I've deprecated it and updated the tests. I'll do a follow-up patch to do some more cleanup and documentation work in this header. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60407 llvm-svn: 358037
* [X86] Fix a dangling StringRef issue introduced in r358029.Craig Topper2019-04-091-3/+4
| | | | | | | | I was attempting to convert mnemonics to lower case after processing a pseudo prefix. But the ParseOperands just hold a StringRef for tokens so there is no where to allocate the memory. Add FIXMEs for the lower case issue which also exists in the prefix parsing code. llvm-svn: 358036
* [AArch64][GlobalISel] Add isel support for vector G_ICMP and G_ASHR & G_SHLAmara Emerson2019-04-091-2/+259
| | | | | | | | | | | | | | | | The selection for G_ICMP is unfortunately not currently importable from SDAG due to the use of custom SDNodes. To support this, this selection method has an opcode table which has been generated by a script, indexed by various instruction properties. Ideally in future we will have a GISel native selection patterns that we can write in tablegen to improve on this. For selection of some types we also need support for G_ASHR and G_SHL which are generated as a result of legalization. This patch also adds support for them, generating the same code as SelectionDAG currently does. Differential Revision: https://reviews.llvm.org/D60436 llvm-svn: 358035
* [AArch64][GlobalISel] Legalize vector G_ICMP.Amara Emerson2019-04-091-2/+27
| | | | | | | | Selection support will be coming in a later patch. Differential Revision: https://reviews.llvm.org/D60435 llvm-svn: 358034
* [AArch64][GlobalISel] Add legalization for some vector G_SHL and G_ASHR.Amara Emerson2019-04-091-4/+6
| | | | | | | | This is needed for some future support for vector ICMP. Differential Revision: https://reviews.llvm.org/D60433 llvm-svn: 358033
* [GlobalISel][AArch64] Allow CallLowering to handle types which are normallyAmara Emerson2019-04-094-15/+106
| | | | | | | | | | | required to be passed as different register types. E.g. <2 x i16> may need to be passed as a larger <2 x i32> type, so formal arg lowering needs to be able truncate it back. Likewise, when dealing with returns of these types, they need to be widened in the appropriate way back. Differential Revision: https://reviews.llvm.org/D60425 llvm-svn: 358032
* [X86] Add support for {vex2}, {vex3}, and {evex} to the assembler to match ↵Craig Topper2019-04-093-9/+111
| | | | | | | | | | | | | | | | gas. Use {evex} to improve the one our 32-bit AVX512 tests. These can be used to force the encoding used for instructions. {vex2} will fail if the instruction is not VEX encoded, but otherwise won't do anything since we prefer vex2 when possible. Might need to skip use of the _REV MOV instructions for this too, but I haven't done that yet. {vex3} will force the instruction to use the 3 byte VEX encoding or fail if there is no VEX form. {evex} will force the instruction to use the EVEX version or fail if there is no EVEX version. Differential Revision: https://reviews.llvm.org/D59266 llvm-svn: 358029
* [DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO ↵Craig Topper2019-04-091-0/+8
| | | | | | | | | | by negating the immediate. This lines up with what we do for regular subtract and it matches up better with X86 assumptions in isel patterns that add with immediate is more canonical than sub with immediate. Differential Revision: https://reviews.llvm.org/D60020 llvm-svn: 358027
* Revert "[InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y)."Nikita Popov2019-04-091-6/+0
| | | | | | | | | | | This reverts commit 1383a9168948aabfd827220c9445ce0ce5765800. sdiv-canonicalize.ll fails after this revision. The fold needs to be moved outside the branch handling constant operands. However when this is done there are further test changes, so I'm reverting this in the meantime. llvm-svn: 358026
* [InstCombine] Restructure OptimizeOverflowCheck; NFCNikita Popov2019-04-091-31/+28
| | | | | | | | | Change the code to always handle the unsigned+signed cases together with the same basic structure for add/sub/mul. The simple folds are always handled first and then the ValueTracking overflow checks are used. llvm-svn: 358025
* [ValueTracking] Use computeConstantRange() for signed sub overflow determinationNikita Popov2019-04-091-6/+4
| | | | | | | | | | This is the same change as D60420 but for signed sub rather than signed add: Range information is intersected into the known bits result, allows to detect more no/always overflow conditions. Differential Revision: https://reviews.llvm.org/D60469 llvm-svn: 358020
* [TargetLowering] SimplifyDemandedBits - add ISD::INSERT_SUBVECTOR supportSimon Pilgrim2019-04-091-0/+39
| | | | llvm-svn: 358019
* [InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y).Chen Zheng2019-04-091-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D60395 llvm-svn: 358017
* Revert LIS handling in MachineDCEStanislav Mekhanoshin2019-04-091-28/+2
| | | | | | | | | | One of out of tree targets has regressed with this patch. Reverting it for now and let liveness to be fully reconstructed in case pass was used after the LIS is created to resolve the regression. Differential Revision: https://reviews.llvm.org/D60466 llvm-svn: 358015
* [ValueTracking] Use computeConstantRange() in signed add overflow determinationNikita Popov2019-04-091-8/+6
| | | | | | | | | | | | | This is D59386 for the signed add case. The computeConstantRange() result is now intersected into the existing known bits information, allowing to detect additional no-overflow/always-overflow conditions (though the latter isn't used yet). This (finally...) covers the motivating case from D59071. Differential Revision: https://reviews.llvm.org/D60420 llvm-svn: 358014
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