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* [sancov] do not instrument nodes that are full pre-dominatorsMike Aizatsky2016-02-271-11/+22
| | | | | | | | | | | Summary: Without tree pruning clang has 2,667,552 points. Wiht only dominators pruning: 1,515,586. With both dominators & predominators pruning: 1,340,534. Differential Revision: http://reviews.llvm.org/D17671 llvm-svn: 262103
* [libFuzzer] speedup path coverage handlingKostya Serebryany2016-02-272-18/+19
| | | | llvm-svn: 262102
* Minor code cleanup. NFC.Junmo Park2016-02-271-1/+1
| | | | llvm-svn: 262096
* [InstCombine] Be more conservative about removing stackrestoreReid Kleckner2016-02-271-1/+7
| | | | | | | We ended up removing a save/restore pair around an inalloca call, leading to a miscompile in Chromium. llvm-svn: 262095
* Fix a bug in isVectorReductionOp() in SelectionDAGBuilder.cpp that may cause ↵Cong Hou2016-02-261-4/+4
| | | | | | assertion failure on AArch64. llvm-svn: 262091
* [X86] Fix a stale comment. NFC.Ahmed Bougacha2016-02-261-2/+2
| | | | llvm-svn: 262087
* [X86] Remove the unused SDTX86atomicBinary. NFC.Ahmed Bougacha2016-02-261-2/+0
| | | | llvm-svn: 262086
* [LVI] Extend select handling to catch min/max/clamp idiomsPhilip Reames2016-02-261-3/+71
| | | | | | | | | | Most of this is fairly straight forward. Add handling for min/max via existing matcher utility and ConstantRange routines. Add handling for clamp by exploiting condition constraints on inputs. Note that I'm only handling two constant ranges at this point. It would be reasonable to consider treating overdefined as a full range if the instruction is typed as an integer, but that should be a separate change. Differential Revision: http://reviews.llvm.org/D17184 llvm-svn: 262085
* [libFuzzer] add -print_final_stats=1 flagKostya Serebryany2016-02-266-3/+41
| | | | llvm-svn: 262084
* Strip trailing whitespace. NFCI.Simon Pilgrim2016-02-262-10/+10
| | | | llvm-svn: 262083
* [ConstantRange] Add umin/smin operatorsPhilip Reames2016-02-261-0/+26
| | | | | | | | This was split off from http://reviews.llvm.org/D17184. Reviewed by: Sanjoy llvm-svn: 262080
* [PPC] Legalize FNEG on PPC when possibleKit Barton2016-02-261-0/+3
| | | | | | | | Currently we always expand ISD::FNEG. For v4f32 and v2f64 vector types VSX has native support for this opcode Phabricator: http://reviews.llvm.org/D17647 llvm-svn: 262079
* Fix spelling. NFCI.Simon Pilgrim2016-02-261-1/+1
| | | | llvm-svn: 262078
* [x86, InstCombine] transform x86 AVX2 masked stores to LLVM intrinsicsSanjay Patel2016-02-261-1/+4
| | | | | | | | | Replicate everything for integers...because x86. Continuation of: http://reviews.llvm.org/rL262064 llvm-svn: 262077
* [libFuzzer] initial implementation of path coverage based on ↵Kostya Serebryany2016-02-267-0/+103
| | | | | | -fsanitize-coverage=trace-pc. This does not scale well yet, but already cracks FullCoverageSetTest in seconds llvm-svn: 262073
* Power9] Implement new vsx instructions: compare and conversionKit Barton2016-02-266-0/+257
| | | | | | | | | | | | | | | | | | | This change implements the following vsx instructions: Quad/Double-Precision Compare: xscmpoqp xscmpuqp xscmpexpdp xscmpexpqp xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp xvcmpnedp(.) xvcmpnesp(.) Quad-Precision Floating-Point Conversion xscvqpdp(o) xscvdpqp xscvqpsdz xscvqpswz xscvqpudz xscvqpuwz xscvsdqp xscvudqp xscvdphp xscvhpdp xvcvhpsp xvcvsphp xsrqpi xsrqpix xsrqpxp 28 instructions Phabricator: http://reviews.llvm.org/D16709 llvm-svn: 262068
* [x86, InstCombine] transform x86 AVX masked stores to LLVM intrinsicsSanjay Patel2016-02-261-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The intended effect of this patch in conjunction with: http://reviews.llvm.org/rL259392 http://reviews.llvm.org/rL260145 is that customers using the AVX intrinsics in C will benefit from combines when the store mask is constant: void mstore_zero_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set1_epi32(0), v); } void mstore_fake_ones_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set1_epi32(1), v); } void mstore_ones_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set1_epi32(0x80000000), v); } void mstore_one_set_elt_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set_epi32(0x80000000, 0, 0, 0), v); } ...so none of the above will actually generate a masked store for optimized code. Differential Revision: http://reviews.llvm.org/D17485 llvm-svn: 262064
* [x86] refactor to eliminate duplicated code; NFCISanjay Patel2016-02-261-23/+12
| | | | llvm-svn: 262062
* Fix warning in DwarfCFIException. NFCAmaury Sechet2016-02-261-1/+1
| | | | llvm-svn: 262061
* Extract the method to begin and end a fragment in AsmPrinterHandler in their ↵Amaury Sechet2016-02-264-12/+43
| | | | | | | | | | | | | | own method. NFC Summary: This is extracted from D17555 Reviewers: davidxl, reames, sanjoy, MatzeB, pete Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17580 llvm-svn: 262058
* [GlobalISel] Fix a ranlib warning about empty TOC.Quentin Colombet2016-02-261-3/+6
| | | | | | Fixes PR26733 llvm-svn: 262057
* Fix Sparc 32bit Lowering to rebundle up v2i32 values.Nirav Dave2016-02-261-4/+23
| | | | | | | | | | | | Summary: Fix LowerCall to rebundle v2i32 values after lowering and add testcase Reviewers: jyknight Subscribers: llvm-commits, jyknight Differential Revision: http://reviews.llvm.org/D17615 llvm-svn: 262048
* [x86, AVX] fold 'isPositive' 256-bit vector integer operations (PR26701)Sanjay Patel2016-02-261-4/+13
| | | | | | | This extends the fold introduced with: http://reviews.llvm.org/rL262036 llvm-svn: 262047
* [IR] Optimize bitfield layout of Value for MSVCReid Kleckner2016-02-261-0/+2
| | | | | | | | | | | | | | | This should save a pointer of padding from all MSVC Value subclasses. Recall that MSVC will not pack the following bitfields together: unsigned Bits : 29; unsigned Flag1 : 1; unsigned Flag2 : 1; unsigned Flag3 : 1; Add a static_assert because LLVM developers always trip over this behavior. This regressed in June. llvm-svn: 262045
* [CMAKE] Update build on recent HaikuRenato Golin2016-02-261-1/+3
| | | | | | | | | This patch updates cmake build scripts to build on Haiku. It adds Haiku x86_64 to config.guess. Please consider reviewing. Pathc by Jérôme Duval. llvm-svn: 262038
* [x86, SSE] fold 'isPositive' vector integer operations (PR26701)Sanjay Patel2016-02-261-0/+42
| | | | | | | | | | | | | This is one of the cases shown in: https://llvm.org/bugs/show_bug.cgi?id=26701 Shift and negate is what InstCombine appears to prefer, so I've started with that pattern. Note that the 'pcmpeq' instructions are always generating the negative one for the actual 'pcmpgt' comparison in each case (side note: why isn't there an alias mnemonic for that?). Differential Revision: http://reviews.llvm.org/D17630 llvm-svn: 262036
* [WinEH] Fix funclet return block clobber mask placementReid Kleckner2016-02-261-2/+6
| | | | | | | | | | | | | | | | | | MBB slot index intervals are half open, not closed. getMBBEndIndex() returns the slot index of the start of the next block in layout order. Placing a register mask there is incorrect if the successor of the funclet return is not laid out after the return. Clang generates IR for catch bodies before generating the following normal code, so we never noticed this issue until the D frontend authors filed a bug about it. Instead, we can put the clobber mask on the last instruction of the funclet return block. We still aren't using a register mask operand on the CATCHRET instruction because it would cause PEI to spill all CSRs, including XMM regs, in the prologue. Fixes PR26679. llvm-svn: 262035
* [PM] Finish removing references to fix MSVC builds. Somehow adding baseChandler Carruth2016-02-261-8/+16
| | | | | | | | | classes changed whether the decltype of these expressions was a reference. I'm somewhat horrified why, and there may need to be a deeper fix on MSVC, but this should at least get the bots a step further. llvm-svn: 262008
* Reverting breaking change. Sorry.Chris Dewhurst2016-02-264-303/+10
| | | | llvm-svn: 262007
* [PM] Speculative patch to try and fix MSVC's compilation.Chandler Carruth2016-02-261-1/+3
| | | | | | No idea why r262004 triggered this, but just trying to fix somehow. llvm-svn: 262006
* Reviewed at reviews.llvm.org/D17133Chris Dewhurst2016-02-264-10/+303
| | | | llvm-svn: 262005
* [PM] Introduce CRTP mixin base classes to help define passes andChandler Carruth2016-02-2623-79/+4
| | | | | | | | | | | | | | | | | analyses in the new pass manager. These just handle really basic stuff: turning a type name into a string statically that is nice to print in logs, and getting a static unique ID for each analysis. Sadly, the format of passes in anonymous namespaces makes using their names in tests really annoying so I've customized the names of the no-op passes to keep tests sane to read. This is the first of a few simplifying refactorings for the new pass manager that should reduce boilerplate and confusion. llvm-svn: 262004
* Initial test commit onlyChris Dewhurst2016-02-261-1/+0
| | | | llvm-svn: 262003
* [AMDGPU] Assembler: Basic support for MIMGNikolay Haustov2016-02-266-59/+202
| | | | | | | | | | | Add parsing and printing of image operands. Matches legacy sp3 assembler. Change image instruction order to have data/image/sampler operands in the beginning. This is needed because optional operands in MC are always last. Update SITargetLowering for new order. Add basic MC test. Update CodeGen tests. Review: http://reviews.llvm.org/D17574 llvm-svn: 261995
* [AArch64] Slight cleanup in FPLoadBalancingJames Molloy2016-02-261-2/+1
| | | | | | | | Instead of the convoluted if-statment we can just use getColor. This also fixes a bug where we relied upon the parity of tablegen-generated register indexes (instead of using the machine encoding). llvm-svn: 261990
* [X86] Null out some redundant patterns for masked vector register to ↵Craig Topper2016-02-261-10/+19
| | | | | | | | register moves. These can be accomplished with both aligned and unaligned opcodes. Currently aligned is what is being used so remove the redundant patterns for the unaligned versions. But don't do this for the byte and word vector types since they don't have aligned versions. llvm-svn: 261985
* [TableGen] Fix typos in comments. NFCCraig Topper2016-02-261-2/+2
| | | | llvm-svn: 261984
* [X86] Add test cases for r261977 and fix a grammatical error.Craig Topper2016-02-261-1/+1
| | | | llvm-svn: 261983
* [JumpThreading] Simplify Instructions first in ComputeValueKnownInPredecessors()Haicheng Wu2016-02-261-20/+35
| | | | | | This change tries to find more opportunities to thread over basic blocks. llvm-svn: 261981
* [X86] Remove a couple returns after llvm_unreachables. NFCCraig Topper2016-02-261-6/+2
| | | | llvm-svn: 261979
* [X86] Use inclusive ranges for XMM/YMM/ZMM registers in is32Extended and ↵Craig Topper2016-02-261-9/+9
| | | | | | isX86_64ExtendedReg. NFC llvm-svn: 261978
* [X86] Explicitly diagnose use of %xmm16-%xmm31, %ymm16-%ymm31 and ↵Craig Topper2016-02-261-1/+7
| | | | | | %zmm16-%zmm31 when AVX512 is not enabled in the asm parser. llvm-svn: 261977
* MachineCopyPropagation: Catch copies of the form A<-B;A<-BMatthias Braun2016-02-261-54/+71
| | | | | | Differential Revision: http://reviews.llvm.org/D17475 llvm-svn: 261966
* MachineCopyPropagation: Keep scanning through instructions with regmasksMatthias Braun2016-02-261-55/+55
| | | | | | | | | | | | | | | | | | | | | | | This also simplifies the code by removing the overly conservative NoInterveningSideEffect() function. This function checked: - That the two copies belong to the same block: We only process one block at a time and clear our maps in between it is impossible to find a copy from a different block. - There is no terminator between the two copy instructions: This is not allowed anyway (the MachineVerifier would complain) - Does not have instructions with hasUnmodeledSideEffects() or isCall() set: Even for those instructuction we must have all clobbers/defs of registers explicit as an operand. If the register is explicitely clobbered we would never come to the point of checking for NoInterveningSideEffect() anyway. (I also checked this with a temporary build of the test-suite with all potentially failing conditions in NoInterveningSideEffect() turned into asserts) Differential Revision: http://reviews.llvm.org/D17474 llvm-svn: 261965
* [LoopUnrollAnalyzer] Check that we're using SCEV for the same loop we're ↵Michael Zolotukhin2016-02-262-2/+2
| | | | | | | | | | | | | | simulating. Summary: Check that we're using SCEV for the same loop we're simulating. Otherwise, we might try to use the iteration number of the current loop in SCEV expressions for inner/outer loops IVs, which is clearly incorrect. Reviewers: chandlerc, hfinkel Subscribers: sanjoy, llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D17632 llvm-svn: 261958
* Minor code cleanups. NFC.Junmo Park2016-02-261-3/+3
| | | | llvm-svn: 261955
* [sancov] Pruning full dominator blocks from instrumentation.Mike Aizatsky2016-02-261-4/+32
| | | | | | | | | | | | | | Summary: This is the first simple attempt to reduce number of coverage- instrumented blocks. If a basic block dominates all its successors, then its coverage information is useless to us. Ingore such blocks if santizer-coverage-prune-tree option is set. Differential Revision: http://reviews.llvm.org/D17626 llvm-svn: 261949
* [WinEH] Don't remove unannotated inline-asm callsDavid Majnemer2016-02-261-2/+3
| | | | | | | | Inline-asm calls aren't annotated with funclet bundle operands because they don't throw and cannot be inlined through. We shouldn't require them to bear an funclet bundle operand. llvm-svn: 261942
* Reformatted a comment to fit the 80 column limit. NFC.David L Kreitzer2016-02-251-2/+2
| | | | llvm-svn: 261916
* Introduce RegionInfoAnalysis, which compute Region Tree in the new ↵Hongbin Zheng2016-02-253-0/+38
| | | | | | | | PassManager. NFC Differential Revision: http://reviews.llvm.org/D17571 llvm-svn: 261904
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