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* AArch64: Fix XSeqPairs/WSeqPairs problemsMatthias Braun2018-10-041-18/+68
| | | | | | | | | | - Fix spill/reloads of XSeqPairs failing with vregs (only physregs worked correctly) - Add missing spill/reload code for WSeqPairs class Differential Revision: https://reviews.llvm.org/D52761 llvm-svn: 343799
* [AMDGPU] Match signed dot4/8 pattern.Farhana Aleen2018-10-041-48/+59
| | | | | | | | | | | | Summary: This patch matches signed dot4 and dot8 pattern. Author: FarhanaAleen Reviewed By: msearles Differential Revision: https://reviews.llvm.org/D52520 llvm-svn: 343798
* [InstCombine] allow bitcast to/from FP for vector insert/extract transformSanjay Patel2018-10-041-4/+31
| | | | | | | | This is a follow-up to rL343482 / D52439. This was a pattern that initially caused the commit to be reverted because the transform requires a bitcast as shown here. llvm-svn: 343794
* [RISCV] Remove overzealous is64Bit checksAlex Bradbury2018-10-042-4/+3
| | | | | | | | lowerGlobalAddress, lowerBlockAddress, and insertIndirectBranch contain overzealous checks for is64Bit. These functions are all safe as-implemented for RV64. llvm-svn: 343781
* [X86] Set correct MMO offset on scalarized load piecesDavid Greene2018-10-041-3/+9
| | | | | | | When scalarizing a load, be sure to update the offset in the MachineMemOperand for each scalar load. llvm-svn: 343776
* [PassTimingInfo] cleanup on TimingData's Timer handlingFedor Sergeev2018-10-041-6/+6
| | | | | | | | Replacing Timer* with unique_ptr<Timer> in a pass-to-timer map. That allows to get rid of unpretty raw deletes in PassTimingInfo destructor. Strictly cleanup, not intended to change any visible behavior. llvm-svn: 343772
* Fix MSVC "not all control paths return a value" warning. NFCI.Simon Pilgrim2018-10-041-0/+1
| | | | llvm-svn: 343765
* [RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32FAlex Bradbury2018-10-041-4/+7
| | | | | | | | | | | | | f32 values passed on the stack would previously cause an assertion in unpackFromMemLoc.. This would only trigger in the presence of the F extension making f32 a legal type. Otherwise the f32 would be legalized. This patch fixes that by keeping LocVT=f32 when a float is passed on the stack. It also adds test coverage for this case, and tests that also demonstrate lw/sw/flw/fsw will be selected when most profitable. i.e. there is no unnecessary i32<->f32 conversion in registers. llvm-svn: 343756
* [X86] Merge matchANDXORWithAllOnesAsANDNP into ↵Craig Topper2018-10-041-25/+12
| | | | | | | | combineANDXORWithAllOnesIntoANDNP. NFCI It's the only caller and the logic pretty easy to combine. llvm-svn: 343754
* [RISCV][NFC] Fix naming of RISCVISelLowering::{LowerRETURNADDR,LowerFRAMEADDR}Alex Bradbury2018-10-042-7/+7
| | | | | | | Rename to lowerRETURNADDR, lowerFRAMEADDR in order to be consistent with the LLVM coding style and the other functions in this file. llvm-svn: 343752
* [LegalizeIntegerTypes] Fix typo in comment. NFCCraig Topper2018-10-041-1/+1
| | | | llvm-svn: 343750
* [RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombineAlex Bradbury2018-10-033-12/+20
| | | | | | | | r343712 performed this optimisation during instruction selection. As Eli Friedman pointed out in post-commit review, implementing this as a DAGCombine might allow opportunities for further optimisations. llvm-svn: 343741
* [WebAssembly] Bitselect intrinsic and instructionThomas Lively2018-10-033-0/+31
| | | | | | | | | | | | Summary: Depends on D52755. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52805 llvm-svn: 343739
* [RISCV][NFC] Refactor LocVT<->ValVT converstion in RISCVISelLoweringAlex Bradbury2018-10-031-40/+33
| | | | | | | | | | There was some duplicated logic for using the LocInfo of a CCValAssign in order to convert from the ValVT to LocVT or vice versa. Resolve this by factoring out convertLocVTFromValVT from unpackFromRegLoc. Also rename packIntoRegLoc to the more appropriate convertValVTToLocVT and call these helper functions consistently. llvm-svn: 343737
* [WebAssembly] Refactor WasmSignature and use it for MCSymbolWasmDerek Schuff2018-10-0312-125/+115
| | | | | | | | | | | | MCContext does not destroy MCSymbols on shutdown. So, rather than putting SmallVectors (which may heap-allocate) inside MCSymbolWasm, use unowned pointer to a WasmSignature instead. The signatures are now owned by the AsmPrinter. Also uses WasmSignature instead of param and result vectors in TargetStreamer, and leaves some TODOs for further simplification. Differential Revision: https://reviews.llvm.org/D52580 llvm-svn: 343733
* [machineverifier] Detect PHI's that are preceeded by non-PHI'sDaniel Sanders2018-10-031-3/+11
| | | | | | | | If present, PHI nodes must appear before non-PHI nodes in a basic block. The register allocator relies on this and will fail to eliminate PHI's that do not meet this requirement. llvm-svn: 343731
* [InstCombine] allow SimplifyDemandedVectorElts to work with FP binopsSanjay Patel2018-10-031-18/+20
| | | | | | | | | | | | | | | | | We're a long way from D50992 and D51553, but this is where we have to start. We weren't back-propagating undefs into binop constant values for anything but add/sub/mul/and/or/xor. This is likely because we have to be careful about not introducing UB/poison with div/rem/shift. But I suspect we already are getting the poison part wrong for add/sub/mul (although it may not be possible to expose the bug currently because we use SimplifyDemandedVectorElts from a limited set of opcodes). See the discussion/implementation from D48987 and D49047. This patch just enables functionality for FP ops because those do not have UB/poison potential. llvm-svn: 343727
* Make meanings of variables clearer in action table generation (NFC)Heejin Ahn2018-10-031-11/+12
| | | | | | | | | | | | Summary: Reviewers: kristina, zhmu, dschuff, rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52680 llvm-svn: 343724
* [X86] Stop promoting vector ISD::SELECT to vXi64.Craig Topper2018-10-032-3/+41
| | | | | | The additional patterns needed for this aren't overwhelming and introducing extra bitcasts during lowering limits our ability to do computeNumSignBits. Not that I have a good example of that for select. I'm just becoming increasingly grumpy about promotion of AND/OR/XOR. SELECT was just a lot easier to fix. llvm-svn: 343723
* [X86] Add CMOV_VK2/VK4 pseudos and remove lowering code that turned ↵Craig Topper2018-10-032-10/+6
| | | | | | v2i1/v4i1 SELECT into v8i1. llvm-svn: 343713
* [RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during ↵Alex Bradbury2018-10-031-39/+12
| | | | | | | | | | | | instruction selection Although we can't write a tablegen pattern to remove redundant splitf64+buildf64 pairs due to the multiple return values, we can handle it with some C++ selection code. This is simpler than removing them after instruction selection through RISCVDAGToDAGISel::PostprocessISelDAG, as was done previously. llvm-svn: 343712
* [X86] Add CMOV pseudos for VR128X and VR256X register classes. Use them when ↵Craig Topper2018-10-032-10/+34
| | | | | | | | AVX512VL is enabled. This allows the phi nodes to be generated with the correct register class when expanded. llvm-svn: 343710
* [X86] Don't break CMOV pseudo instructions down by type. Just by register class.Craig Topper2018-10-032-41/+36
| | | | | | The register class is all that's important for the pseudo instructions. We can use patterns to handle the different types. llvm-svn: 343709
* [X86] PUSH/POP 'mem-mem' instructions are not RMW - these are 2 different ↵Simon Pilgrim2018-10-032-5/+6
| | | | | | | | | | addresses This patch adds a 'WriteCopy' [WriteLoad, WriteStore] schedule sequence instead to better model the behaviour Found by @andreadb during llvm-mca testing on btver2 which was crashing on "zero uop" WriteRMW only instructions llvm-svn: 343708
* Emit template type and value parameter DIEs for template variables.Matthew Voss2018-10-039-60/+78
| | | | | | | | | | | | | | | | | | | Summary: Ensure the TemplateParam attribute of the DIGlobalVariable node is translated into the proper DIEs. Resolves https://bugs.llvm.org/show_bug.cgi?id=22119 Reviewers: dblaikie, probinson, aprantl, JDevlieghere, clayborg, whitequark, deadalnix Reviewed By: dblaikie Subscribers: llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D52057 llvm-svn: 343706
* [X86] Move Atomic binops to use WriteALURMW schedule classSimon Pilgrim2018-10-031-4/+4
| | | | | | These were being tagged as <WriteALULd, WriteRMW> instead of properly using the RMW sequence llvm-svn: 343705
* [X86][Btver2] Fix MMX PSHUFB scheduleSimon Pilgrim2018-10-031-1/+1
| | | | | | Match AMD Fam16h SOG + llvm-exegesis tests llvm-svn: 343701
* [X86] Move Atomic CMPXCHG to WriteCMPXCHGRMW schedule classSimon Pilgrim2018-10-031-5/+5
| | | | llvm-svn: 343700
* [X86] Add SkylakeClient uops counter - same as the other Intel models.Simon Pilgrim2018-10-031-0/+1
| | | | llvm-svn: 343697
* Correct implementation of -verify-machineinstrs such that it's still ↵Daniel Sanders2018-10-031-5/+5
| | | | | | | | | | | overridable for EXPENSIVE_CHECKS -verify-machineinstrs was implemented as a simple bool. As a result, the 'VerifyMachineCode == cl::BOU_UNSET' used by EXPENSIVE_CHECKS to make it on by default but possible to disable didn't work as intended. Changed -verify-machineinstrs to a boolOrDefault to correct this. llvm-svn: 343696
* [InstCombine] clean up foldVectorBinop(); NFCSanjay Patel2018-10-031-11/+12
| | | | | | | | 1. Fix include ordering. 2. Improve variable name (width is bitwidth not number-of-elements). 3. Add local Opcode variable to reduce code duplication. llvm-svn: 343694
* [globalisel][combines] Don't sink G_TRUNC down to use if that use is a G_PHIDaniel Sanders2018-10-031-2/+8
| | | | | | | | | | | | This fixes a problem where the register allocator fails to eliminate a PHI because there's a non-PHI in the middle of the PHI instructions at the start of a BB. This G_TRUNC can be better placed but this at least fixes the correctness issue quickly. I'll follow up with a patch to the verifier to catch this kind of bug in future. llvm-svn: 343693
* [InstCombine] name change: foldShuffledBinop -> foldVectorBinop; NFCSanjay Patel2018-10-036-20/+20
| | | | | | | This function will deal with more than shuffles with D50992, and I have another potential per-element fold that could live here. llvm-svn: 343692
* [X86] Correctly use SSE registers if no-x87 is selected.Nirav Dave2018-10-031-28/+36
| | | | | | | | | | | | | | | | | | | | Fix use of SSE1 registers for f32 ops in no-x87 mode. Notably, allow use of SSE instructions for f32 operations in 64-bit mode (but not 32-bit which is disallowed by callign convention). Also avoid translating memset/memcopy/memmove into SSE registers without X87 for 32-bit mode. This fixes PR38738. Reviewers: nickdesaulniers, craig.topper Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D52555 llvm-svn: 343689
* [RISCV][NFC] Refactor RISCVDAGToDAGISel::SelectAlex Bradbury2018-10-031-12/+12
| | | | | | Introduce and use a switch on the opcode. llvm-svn: 343688
* [RA CopyHints] Fix compile-time regressionJonas Paulsson2018-10-031-2/+4
| | | | | | | | | | | This patch makes sure that a register is only hinted once to RA. In extreme cases the same register can otherwise be hinted numerous times and cause a compile time slowdown. Review: Simon Pilgrim https://reviews.llvm.org/D52826 llvm-svn: 343686
* [RISCV] Gate float<->int and double<->int conversion patterns on IsRV32Alex Bradbury2018-10-032-14/+24
| | | | | | | | | The patterns as defined are correct only when XLen==32. This is another preparatory patch for a set of patches that flesh out RV64 codegen. llvm-svn: 343679
* [RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo tdAlex Bradbury2018-10-032-11/+11
| | | | | | | | | 1. brcond operates on an condition. 2. atomic_fence and the pseudo AMO instructions should all take xlen immediates This allows the same definitions and patterns to work for RV64 (XLenVT==i64). llvm-svn: 343678
* [RISCV] Gate simm32 materialisation pattern and SW pattern on IsRV32Alex Bradbury2018-10-031-2/+3
| | | | | | These patterns are not correct for RV64. llvm-svn: 343677
* [LoopInterchange] Remove unused variable PreserveLCSSA (NFC).Florian Hahn2018-10-031-1/+0
| | | | llvm-svn: 343676
* [CodeGen] NFC fix pedantic warning from extra semicolonJonas Toth2018-10-031-1/+1
| | | | llvm-svn: 343674
* [AMDGPU] Fix for negative offsets in buffer/tbuffer intrinsicsTim Renouf2018-10-031-1/+8
| | | | | | | | | | | | | | | | | | | Summary: The new buffer/tbuffer intrinsics handle an out-of-range immediate offset by moving/adding offset&-4096 to a vgpr, leaving an in-range immediate offset, with a chance of the move/add being CSEd for similar loads/stores. However it turns out that a negative offset in a vgpr is illegal, even if adding the immediate offset makes it legal again. Therefore, this commit disables the offset&-4096 thing if the offset is negative. Differential Revision: https://reviews.llvm.org/D52683 Change-Id: Ie02f0a74f240a138dc2a29d17cfbd9e350e4ed13 llvm-svn: 343672
* [X86][Btver2] Most RMW instructions don't require an additional uopSimon Pilgrim2018-10-031-4/+5
| | | | | | | | Remove uop on WriteRMW and move it into the few instructions that need it. Match AMD Fam16h SOG + llvm-exegesis tests llvm-svn: 343671
* [X86] ALU/ADC RMW instructions should use the WriteRMW sequence classSimon Pilgrim2018-10-031-2/+2
| | | | | | | | | | | | | I was expecting this to be a nfc but Silvermont seems to be setup a little differently: // A folded store needs a cycle on MEC_RSV for the store data, but it does not need an extra port cycle to recompute the address. def : WriteRes<WriteRMW, [SLM_MEC_RSV]>; So moving from WriteStore to WriteRMW reduces predicted port pressure, confirmed by @craig.topper that this is correct. Differential Revision: https://reviews.llvm.org/D52740 llvm-svn: 343670
* Improve static analysis of cold basic blocksAditya Kumar2018-10-031-1/+14
| | | | | | | | | Differential Revision: https://reviews.llvm.org/D52704 Reviewers: sebpop, tejohnson, brzycki, SirishP Reviewed By: sebpop llvm-svn: 343663
* Add support for new pass managerAditya Kumar2018-10-033-0/+40
| | | | | | | | | | | Modified the testcases to use both pass managers Use single commandline flag for both pass managers. Differential Revision: https://reviews.llvm.org/D52708 Reviewers: sebpop, tejohnson, brzycki, SirishP Reviewed By: tejohnson, brzycki llvm-svn: 343662
* [AMDGPU] Rename pass "isel" to "amdgpu-isel"Fangrui Song2018-10-031-2/+2
| | | | | | | | | | | | | | Summary: The AMDGPU target specific pass "isel" is a misleading name. Reviewers: tstellar, echristo, javed.absar, arsenm Reviewed By: arsenm Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D52759 llvm-svn: 343659
* AMDGPU: Always run AMDGPUAlwaysInlineMatt Arsenault2018-10-031-12/+9
| | | | | | | Even if calls are enabled, it still needs to be run for forcing inline of functions that use LDS. llvm-svn: 343657
* Add atomicrmw operation to error messagesMatt Arsenault2018-10-032-5/+12
| | | | llvm-svn: 343656
* Add the missing new files from r343654Daniel Sanders2018-10-031-0/+108
| | | | llvm-svn: 343655
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