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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-10-03 10:01:13 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-10-03 10:01:13 +0000 |
| commit | d11015861c370105d05931c7cfecbf35e6da26e8 (patch) | |
| tree | e777635dc7a607c7fd45d7c3ec56af4f61e3258a /llvm/lib | |
| parent | db2e641fd76799b5877c614c3db165a92e7e5dfb (diff) | |
| download | bcm5719-llvm-d11015861c370105d05931c7cfecbf35e6da26e8.tar.gz bcm5719-llvm-d11015861c370105d05931c7cfecbf35e6da26e8.zip | |
[X86] ALU/ADC RMW instructions should use the WriteRMW sequence class
I was expecting this to be a nfc but Silvermont seems to be setup a little differently:
// A folded store needs a cycle on MEC_RSV for the store data, but it does not need an extra port cycle to recompute the address.
def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
So moving from WriteStore to WriteRMW reduces predicted port pressure, confirmed by @craig.topper that this is correct.
Differential Revision: https://reviews.llvm.org/D52740
llvm-svn: 343670
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86Schedule.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index d226d448f14..40884221d1f 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -111,8 +111,8 @@ def WriteMove : SchedWrite; // Arithmetic. defm WriteALU : X86SchedWritePair; // Simple integer ALU op. defm WriteADC : X86SchedWritePair; // Integer ALU + flags op. -def WriteALURMW : WriteSequence<[WriteALULd, WriteStore]>; -def WriteADCRMW : WriteSequence<[WriteADCLd, WriteStore]>; +def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>; +def WriteADCRMW : WriteSequence<[WriteADCLd, WriteRMW]>; def WriteLEA : SchedWrite; // LEA instructions can't fold loads. // Integer multiplication |
