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authorSanjay Patel <spatel@rotateright.com>2018-10-03 21:44:59 +0000
committerSanjay Patel <spatel@rotateright.com>2018-10-03 21:44:59 +0000
commitcafdeb1aa64e4437c93da9fa7e0cc1b81dd89433 (patch)
tree4283cb12fb281bf705cd6c8a943a02108fdb88e5 /llvm/lib
parent0e99f561e1fc419eb5d67a8b7f4a1149906fff4f (diff)
downloadbcm5719-llvm-cafdeb1aa64e4437c93da9fa7e0cc1b81dd89433.tar.gz
bcm5719-llvm-cafdeb1aa64e4437c93da9fa7e0cc1b81dd89433.zip
[InstCombine] allow SimplifyDemandedVectorElts to work with FP binops
We're a long way from D50992 and D51553, but this is where we have to start. We weren't back-propagating undefs into binop constant values for anything but add/sub/mul/and/or/xor. This is likely because we have to be careful about not introducing UB/poison with div/rem/shift. But I suspect we already are getting the poison part wrong for add/sub/mul (although it may not be possible to expose the bug currently because we use SimplifyDemandedVectorElts from a limited set of opcodes). See the discussion/implementation from D48987 and D49047. This patch just enables functionality for FP ops because those do not have UB/poison potential. llvm-svn: 343727
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp38
1 files changed, 20 insertions, 18 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index ad636594bb7..1b5e28ff17f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1378,24 +1378,6 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
}
break;
}
- case Instruction::And:
- case Instruction::Or:
- case Instruction::Xor:
- case Instruction::Add:
- case Instruction::Sub:
- case Instruction::Mul:
- // div/rem demand all inputs, because they don't want divide by zero.
- TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts, UndefElts,
- Depth + 1);
- if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
- TmpV = SimplifyDemandedVectorElts(I->getOperand(1), DemandedElts,
- UndefElts2, Depth + 1);
- if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
-
- // Output elements are undefined if both are undefined. Consider things
- // like undef&0. The result is known zero, not undef.
- UndefElts &= UndefElts2;
- break;
case Instruction::FPTrunc:
case Instruction::FPExt:
TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts, UndefElts,
@@ -1647,5 +1629,25 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
break;
}
}
+
+ // TODO: We bail completely on integer div/rem and shifts because they have
+ // UB/poison potential, but that should be refined.
+ BinaryOperator *BO;
+ if (match(I, m_BinOp(BO)) && !BO->isIntDivRem() && !BO->isShift()) {
+ TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts, UndefElts,
+ Depth + 1);
+ if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
+ TmpV = SimplifyDemandedVectorElts(I->getOperand(1), DemandedElts,
+ UndefElts2, Depth + 1);
+ if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
+
+ // TODO: If this is a potentially poison-producing instruction, we need
+ // to drop the wrapping/exact flags?
+
+ // Output elements are undefined if both are undefined. Consider things
+ // like undef&0. The result is known zero, not undef.
+ UndefElts &= UndefElts2;
+ }
+
return MadeChange ? I : nullptr;
}
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