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* Reorder includes to be sorted.Eric Christopher2014-06-101-1/+1
| | | | llvm-svn: 210578
* Revert "Patch by Ray Donnelly to print register names instead of numbers."Reid Kleckner2014-06-101-11/+4
| | | | | | | | | | | | | This reverts commit r206683. The code was confusing SEH register numbers with DWARF register numbers. The test case it was committed with was obviously incorrect. The disassembler was roundtripping '.seh_pushreg %rsi' as '.seh_pushreg %rbp', and other exciting things. Noticed by Vadim Chugunov. llvm-svn: 210574
* Fix error in tablegen when either operand of !if is an empty list.Matt Arsenault2014-06-102-7/+9
| | | | | | !if([Something], []) would error with "No type for list". llvm-svn: 210572
* Fix typos.Eric Christopher2014-06-101-1/+1
| | | | llvm-svn: 210571
* R600: Use BCNT_INT for evergreenMatt Arsenault2014-06-104-5/+16
| | | | llvm-svn: 210569
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-105-1/+64
| | | | llvm-svn: 210568
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-106-11/+27
| | | | llvm-svn: 210567
* R600: Handle fcopysignMatt Arsenault2014-06-105-3/+27
| | | | llvm-svn: 210564
* R600/SI: Handle sign_extend and zero_extend to i64 with patterns.Matt Arsenault2014-06-103-42/+36
| | | | llvm-svn: 210563
* Add a FIXME.Eric Christopher2014-06-101-0/+2
| | | | llvm-svn: 210559
* Move AArch64SelectionDAGInfo down to the subtarget.Eric Christopher2014-06-104-4/+6
| | | | llvm-svn: 210557
* [FastISel] Collect statistics about failing intrinsic calls.Juergen Ributzka2014-06-101-1/+50
| | | | | | | Add more instruction-specific statistics about failing intrinsic calls during FastISel. llvm-svn: 210556
* Remove the cached little endian variable. We can get it easily offEric Christopher2014-06-102-7/+4
| | | | | | of the DataLayout. llvm-svn: 210555
* Have AArch64SelectionDAGInfo take a DataLayout parameter ratherEric Christopher2014-06-103-4/+4
| | | | | | than a TargetMachine. llvm-svn: 210554
* Remove caching of the subtarget for AArch64SelectionDAGInfo.Eric Christopher2014-06-102-7/+4
| | | | llvm-svn: 210553
* Move DataLayout onto the AArch64 subtarget.Eric Christopher2014-06-104-11/+15
| | | | llvm-svn: 210552
* Test commit, wraps some lines to fit in 80 columns.Zachary Turner2014-06-101-2/+4
| | | | llvm-svn: 210551
* Move AArch64FrameLowering into the subtarget.Eric Christopher2014-06-104-5/+11
| | | | llvm-svn: 210549
* Remove the uses of AArch64TargetMachine and AArch64Subtarget fromEric Christopher2014-06-105-16/+9
| | | | | | AArch64FrameLowering. llvm-svn: 210548
* Do Materialize Floating Point in Mips Fast-IselReed Kotler2014-06-101-2/+23
| | | | | | | | | | | | | | | | | Summary: Implement materialize of floating point literals in Mips Fast-Isel Reopened version of D3659 Test Plan: simplestorefp1.ll Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4071 llvm-svn: 210546
* [X86] Improved target combine rules for selecting horizontal add/sub.Andrea Di Biagio2014-06-101-2/+20
| | | | | | | | | | | | | This patch slightly changes the algorithm introduced at revision 210477 to fix a problem where the algorithm was producing incorrect code for the VEX.256 encoded versions of horizontal add/sub. For these cases, we now try to split the two 256-bit vectors into 128-bit chunks before emitting horizontal add/sub dag nodes. Added a new test case into haddsub-2.ll. llvm-svn: 210545
* Hexagon: Expand i1 SELECT_CCTom Stellard2014-06-101-0/+1
| | | | | | | | il is legal for Hexagon, so I should have marked this as Expand for SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in r210541. llvm-svn: 210544
* [X86] AVX512: Add vmovntdqaAdam Nemet2014-06-101-0/+11
| | | | | | Along with the corresponding intrinsic and tests. llvm-svn: 210543
* Fix a bug in the Thumb1 ARM Load/Store optimizerRenato Golin2014-06-101-7/+7
| | | | | | | | | | | | | | Previously, the basic block was searched for future uses of the base register, and if necessary any writeback to the base register was reset using a SUB instruction (e.g. before calling a function) just before such a use. However, this step happened *before* the merged LDM/STM instruction was built. So if there was (e.g.) a function call directly after the not-yet-formed LDM/STM, the pass would first insert a SUB instruction to reset the base register, and then (at the same location, incorrectly) insert the LDM/STM itself. This patch fixes PR19972. Patch by Moritz Roth. llvm-svn: 210542
* SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CCTom Stellard2014-06-106-28/+22
| | | | | | | | | | | | | The SelectionDAG bad a special case for ISD::SELECT_CC, where it would allow targets to specify: setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); to indicate that they wanted to expand ISD::SELECT_CC for all types. This wasn't applied correctly everywhere, and it makes writing new DAG patterns with ISD::SELECT_CC difficult. llvm-svn: 210541
* SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for ↵Tom Stellard2014-06-101-4/+4
| | | | | | | | | | vectors This prevents a future commit from regressing: test/CodeGen/R600/setcc-equivalent.ll llvm-svn: 210540
* SelectionDAG: Expand SELECT_CC to SELECT + SETCCTom Stellard2014-06-107-52/+24
| | | | | | | | This consolidates code from the Hexagon, R600, and XCore targets. No functionality change intended. llvm-svn: 210539
* [PPC64LE] Recognize shufflevector patterns for little endianBill Schmidt2014-06-103-84/+151
| | | | | | | | | | | | | | | | | Various masks on shufflevector instructions are recognizable as specific PowerPC instructions (vector pack, vector merge, etc.). There is existing code in PPCISelLowering.cpp to recognize the correct patterns for big endian code. The masks for these instructions are different for little endian code due to the big-endian numbering employed by these instructions. This patch adds the recognition code for little endian. I've added a new test case test/CodeGen/PowerPC/vec_shuffle_le.ll for this. The existing recognizer test (vec_shuffle.ll) is unnecessarily verbose and difficult to read, so I felt it was better to add a new test rather than modify the old one. llvm-svn: 210536
* [AArch64] Emit .ident compiler version attribute.Chad Rosier2014-06-101-0/+2
| | | | | | Patch by Ana Pazos<apazos@codeaurora.org>! llvm-svn: 210535
* Condition codes AL and NV are invalid in the aliases that useArtyom Skrobov2014-06-102-1/+10
| | | | | | | | | | | | | | inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM). Matching aliases based on "immediate classes", when disassembling, wasn't previously supported, hence adding MCOperandPredicate into class Operand, and implementing the support for it in AsmWriterEmitter. The parsing for those aliases was already custom, so just adding the missing condition into AArch64AsmParser::parseCondCode. llvm-svn: 210528
* Anonymous definitions in foreach blocks triggered a 'def already exists'Artyom Skrobov2014-06-101-2/+7
| | | | llvm-svn: 210526
* AArch64: disallow x30 & x29 as the destination for indirect tail callsTim Northover2014-06-101-1/+1
| | | | | | | | As Ana Pazos pointed out, these have to be restored to their incoming values before a function returns; i.e. before the tail call. So they can't be used correctly as the destination register. llvm-svn: 210525
* Revert "X86: elide comparisons after cmpxchg instructions."Tim Northover2014-06-102-106/+57
| | | | | | | This reverts commit r210523. It was committed prematurely without waiting for review. llvm-svn: 210524
* X86: elide comparisons after cmpxchg instructions.Tim Northover2014-06-102-57/+106
| | | | | | | | | | | | | | | The C++ and C semantics of the compare_and_swap operations actually require us to return a boolean "success" value. In LLVM terms this means a second comparison of the output of "cmpxchg" against the input desired value. However, x86's "cmpxchg" instruction sets all flags for the comparison formed, so we can skip any secondary comparison. (N.b. this isn't true for cmpxchg8b/16b, which only set ZF). rdar://problem/13201607 llvm-svn: 210523
* AArch64: teach FastISel how to handle offset FrameIndicesTim Northover2014-06-101-4/+11
| | | | | | | | | | Previously we were abandonning the attempt, leading to some combination of extra work (when selection of a load/store fails completely) and inferior code (when this leads to a real memcpy call instead of inlining). rdar://problem/17187463 llvm-svn: 210520
* AArch64: make FastISel memcpy emission more robust.Tim Northover2014-06-101-3/+5
| | | | | | | | | | We were hitting an assert if FastISel couldn't create the load or store we requested. Currently this happens for large frame-local addresses, though CodeGen could be improved there. rdar://problem/17187463 llvm-svn: 210519
* Delete X86JITInfo in the subtarget destructor.Eric Christopher2014-06-101-0/+1
| | | | llvm-svn: 210516
* [ConstantHoisting][X86] Improve the cost model for small constants with ↵Juergen Ributzka2014-06-101-8/+35
| | | | | | | | | | | large types (i64 and above). This improves the X86 cost model for small constants with large types. Before this commit we would even hoist trivial constants such as i96 2. This is related to <rdar://problem/17070936> llvm-svn: 210504
* Reorder Value and User fields to save 8 bytes of padding on 64-bitReid Kleckner2014-06-091-4/+3
| | | | | | | | Reviewered by: rafael Differential Revision: http://reviews.llvm.org/D4073 llvm-svn: 210501
* Removing an "if (!this)" check from two print methods. The condition willRichard Trieu2014-06-098-10/+12
| | | | | | | never be true in a well-defined context. The checking for null pointers has been moved into the caller logic so it does not rely on undefined behavior. llvm-svn: 210497
* [PPC64LE] Generate correct code for unaligned little-endian vector loadsBill Schmidt2014-06-091-21/+39
| | | | | | | | | | | | | | | | | | | The code in PPCTargetLowering::PerformDAGCombine() that handles unaligned Altivec vector loads generates a lvsl followed by a vperm. As we've seen in numerous other places, the vperm instruction has a big-endian bias, and this is fixed for little endian by complementing the permute control vector and swapping the input operands. In this case the lvsl is providing the permute control vector. Rather than generating an lvsl and a complement operation, it is sufficient to generate an lvsr instruction instead. Thus for LE code generation we will generate an lvsr rather than an lvsl, and swap the other input arguments on the vperm. The existing test/CodeGen/PowerPC/vec_misalign.ll is updated to test the code generation for PPC64 and PPC64LE, in addition to the existing PPC32/G5 testing. llvm-svn: 210493
* Generate better location ranges for some register-described variables.Alexey Samsonov2014-06-091-24/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't terminate location ranges for register-described variables at the end of machine basic block if this register is never modified in the function body, except for the prologue and epilogue. Prologue location is guessed by FrameSetup flags on MachineInstructions, while epilogue location is deduced from debug locations of instructions in the basic blocks ending with return instructions. This patch is mostly targeted to fix non-trivial debug locations for variables addressed via stack and frame pointers. It is not really a generic fix. We can still produce poor debug info for register-described variables if this register *is* modified somewhere in the function, but in unrelated places. This might be the case for the debug info in optimized binaries (e.g. for local variables in inlined functions). LiveDebugVariables pass in CodeGen attempts to fix this problem by adjusting DBG_VALUE instructions, but this pass is tied to greedy register allocator, which is used in optimized builds only. Proper fix would likely involve generalizing LiveDebugVariables to all register allocators. See more discussion in http://reviews.llvm.org/D3933 review thread. I'm proceeding with this patch to fix immediate severe problems and important cases, e.g. fix completely broken debug info with AddressSanitizer and fix PR19307 (missing debug info for by-value std::string arguments). llvm-svn: 210492
* ARM: add VLA extension for WoA Itanium ABISaleem Abdulrasool2014-06-093-1/+125
| | | | | | | | | | | | | | | | The armv7-windows-itanium environment is nearly identical to the MSVC ABI. It has a few divergences, mostly revolving around the use of the Itanium ABI for C++. VLA support is one of the extensions that are amongst the set of the extensions. This adds support for proper VLA emission for this environment. This is somewhat similar to the handling for __chkstk emission on X86 and the large stack frame emission for ARM. The invocation style for chkstk is still controlled via the -mcmodel flag to clang. Make an explicit note that this is an extension. llvm-svn: 210489
* Look through addrspacecasts when turning ptr comparisons intoMatt Arsenault2014-06-091-5/+21
| | | | | | index comparisons. llvm-svn: 210488
* Remove old fenv.h workaround for a historic clang driver bugAlp Toker2014-06-091-9/+2
| | | | | | | | | | | Tested and works fine with clang using libstdc++. All indications are that this was fixed some time ago and isn't a problem with any clang version we support. I've added a note in PR6907 which is still open for some reason. llvm-svn: 210485
* Fold FEnv.h into the implementationAlp Toker2014-06-091-7/+41
| | | | | | | | | | | | | | | | | | Support headers shouldn't use config.h definitions, and they should never be undefined like this. ConstantFolding.cpp was the only user of this facility and already includes config.h for other math features, so it makes sense to move the checks there at point of use. (The implicit config.h was also quite dangerous -- removing the FEnv.h include would have silently disabled math constant folding without causing any tests to fail. Need to investigate -Wundef once the cleanup is done.) This eliminates the last config.h include from LLVM headers, paving the way for more consistent configuration checks. llvm-svn: 210483
* Move all of the x86 subtarget initialized variables down into the x86 subtargetEric Christopher2014-06-097-67/+95
| | | | | | from the x86 target machine. Should be no functional change. llvm-svn: 210479
* R600/SI: Rename VOP3 helper class to be more generalMatt Arsenault2014-06-092-4/+4
| | | | | | It has other uses besides shift instructions. llvm-svn: 210478
* [X86] Add target combine rules for horizontal add/sub.Andrea Di Biagio2014-06-092-0/+106
| | | | | | | | | | | | | | | | | | | | This patch adds new target specific combine rules to identify horizontal add/sub idioms from BUILD_VECTOR dag nodes. This patch also teaches the DAGCombiner how to canonicalize sequences of insert_vector_elt dag nodes according to the following rule: (insert_vector_elt (insert_vector_elt A, I0), I1) -> (insert_vecto_elt (insert_vector_elt A, I1), I0) This new canonicalization rule only triggers if the inner insert_vector dag node has exactly one use; also, both indices must be known constants, and I1 < I0. This last rule made it possible to write a simpler algorithm to identify horizontal add/sub patterns because now we don't have to worry about the ordering of insert_vector_elt dag nodes. llvm-svn: 210477
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-093-10/+69
| | | | llvm-svn: 210476
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