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| author | Reed Kotler <rkotler@mips.com> | 2014-06-10 16:45:44 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2014-06-10 16:45:44 +0000 |
| commit | 063d4fba36f152a052afb97bc3a6eef4a283dad9 (patch) | |
| tree | be1036f2d80be6e8de6f41582120ed09533122cf /llvm/lib | |
| parent | fa508af0fec7a6efda5ae1be2dac4c43b4a0dfc8 (diff) | |
| download | bcm5719-llvm-063d4fba36f152a052afb97bc3a6eef4a283dad9.tar.gz bcm5719-llvm-063d4fba36f152a052afb97bc3a6eef4a283dad9.zip | |
Do Materialize Floating Point in Mips Fast-Isel
Summary:
Implement materialize of floating point literals in Mips Fast-Isel
Reopened version of D3659
Test Plan: simplestorefp1.ll
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D4071
llvm-svn: 210546
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsFastISel.cpp | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp index 448698e2de4..9a60aa7b9f4 100644 --- a/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -167,9 +167,14 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr, // // more cases will be handled here in following patches. // - if (VT != MVT::i32) + if (VT == MVT::i32) + EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset); + else if (VT == MVT::f32) + EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset); + else if (VT == MVT::f64) + EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset); + else return false; - EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset); return true; } @@ -229,6 +234,22 @@ bool MipsFastISel::TargetSelectInstruction(const Instruction *I) { } unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) { + int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); + if (VT == MVT::f32) { + const TargetRegisterClass *RC = &Mips::FGR32RegClass; + unsigned DestReg = createResultReg(RC); + unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass); + EmitInst(Mips::MTC1, DestReg).addReg(TempReg); + return DestReg; + } else if (VT == MVT::f64) { + const TargetRegisterClass *RC = &Mips::AFGR64RegClass; + unsigned DestReg = createResultReg(RC); + unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); + unsigned TempReg2 = + Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); + EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); + return DestReg; + } return 0; } |

