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* [MIPS GlobalISel] MSA vector generic and builtin fadd, fsub, fmul, fdivPetar Avramovic2019-10-242-3/+28
| | | | | | | | | | | Select vector G_FADD, G_FSUB, G_FMUL and G_FDIV for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_fadd_<format>, __builtin_msa_fsub_<format>, __builtin_msa_fmul_<format> and __builtin_msa_fdiv_<format> will be transformed into G_FADD, G_FSUB, G_FMUL and G_FDIV in legalizeIntrinsic respectively and selected in the same way. Differential Revision: https://reviews.llvm.org/D69340
* [MIPS GlobalISel] MSA vector generic and builtin sdiv, srem, udiv, uremPetar Avramovic2019-10-242-6/+32
| | | | | | | | | | | Select vector G_SDIV, G_SREM, G_UDIV and G_UREM for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_div_s_<format>, __builtin_msa_mod_s_<format>, __builtin_msa_div_u_<format> and __builtin_msa_mod_u_<format> will be transformed into G_SDIV, G_SREM, G_UDIV and G_UREM in legalizeIntrinsic respectively and selected in the same way. Differential Revision: https://reviews.llvm.org/D69333
* [AMDGPU] Allow folding of sgpr to vgpr copyStanislav Mekhanoshin2019-10-231-2/+3
| | | | | | | | Potentially sgpr to sgpr copy should also be possible. That is however trickier because we may end up with a wrong register class at use because of xm0/xexec permutations. Differential Revision: https://reviews.llvm.org/D69280
* [Hexagon] Fix typo. NFCShoaib Meenai2019-10-231-1/+1
| | | | Testing git push access.
* [mips] Use `expandLoadAddress` for JAL expansionSimon Atanasyan2019-10-231-47/+9
| | | | | - Reduce code duplication - Get partial support of JAL expansion for XGOT.
* [mips] Implement `la` macro expansion for N32 ABISimon Atanasyan2019-10-231-1/+1
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* [X86] combineX86ShufflesRecursively - assert the root mask is legal. NFCI.Simon Pilgrim2019-10-231-0/+3
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* [Mips] Use appropriate private label prefix based on Mips ABIMirko Brkusanin2019-10-2327-37/+62
| | | | | | | | | | MipsMCAsmInfo was using '$' prefix for Mips32 and '.L' for Mips64 regardless of -target-abi option. By passing MCTargetOptions to MCAsmInfo we can find out Mips ABI and pick appropriate prefix. Tags: #llvm, #clang, #lldb Differential Revision: https://reviews.llvm.org/D66795
* [DebugInfo] Stop describing imms in TargetInstrInfo's describeLoadedValue() implDavid Stenberg2019-10-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The default implementation of the describeLoadedValue() hook uses the MoveImm property to determine if an instruction moves an immediate. If an instruction has that property the function returns the second operand, assuming that that is the immediate value the instruction moves. As far as I can tell, the MoveImm property does not imply that the second operand is the immediate value, nor that any other operand necessarily holds the immediate value; it just means that the instruction moves some immediate value. One example where the second operand is not the immediate is SystemZ's LZER instruction, which moves a zero immediate implicitly: $f0S = LZER. That case triggered an out-of-bound assertion when getting the operand. I have added a test case for that instruction. Another example is ARM's MVN instruction, which holds the logical bitwise NOT'd value of the immediate that is moved. For the following reproducer: extern void foo(int); int main() { foo(-11); } an incorrect call site value would be emitted: $ clang --target=arm foo.c -O1 -g -Xclang -femit-debug-entry-values \ -c -o - | ./build/bin/llvm-dwarfdump - | \ grep -A2 call_site_parameter 0x00000058: DW_TAG_GNU_call_site_parameter DW_AT_location (DW_OP_reg0 R0) DW_AT_GNU_call_site_value (DW_OP_lit10) Another example is the A2_combineii instruction on Hexagon which moves two immediates to a super-register: $d0 = A2_combineii 20, 10. Perhaps these are rare exceptions, and most MoveImm instructions hold the immediate in the second operand, but in my opinion the default implementation of the hook should only describe values that it can, by some contract, guarantee are safe to describe, rather than leaving it up to the targets to override the exceptions, as that can silently result in incorrect call site values. This patch adds X86's relevant move immediate instructions to the target's hook implementation, so this commit should be a NFC for that target. We need to do the same for ARM and AArch64. Reviewers: djtodoro, NikolaPrica, aprantl, vsk Reviewed By: vsk Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D69109
* [MIPS GlobalISel] Select MSA vector generic and builtin mulPetar Avramovic2019-10-233-7/+10
| | | | | | | | | | Select vector G_MUL for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. Manual selection of G_MUL is now done for gprb only. __builtin_msa_mulv_<format> will be transformed into G_MUL in legalizeIntrinsic and selected in the same way. Differential Revision: https://reviews.llvm.org/D69310
* [MIPS GlobalISel] Select MSA vector generic and builtin subPetar Avramovic2019-10-232-3/+16
| | | | | | | | | | | Select vector G_SUB for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_subv_<format> will be transformed into G_SUB in legalizeIntrinsic and selected in the same way. __builtin_msa_subvi_<format> will be directly selected into SUBVI_<format> in legalizeIntrinsic. Differential Revision: https://reviews.llvm.org/D69306
* [RISCV] Add support for -ffixed-xX flagsSimon Cook2019-10-228-0/+79
| | | | | | | | | | | This adds support for reserving GPRs such that the compiler will not choose a register for register allocation. The implementation follows the same design as for AArch64; each reserved register becomes a target feature and used for getting the reserved registers for a given MachineFunction. The backend checks that it does not need to write to any reserved register; if it does a relevant error is generated. Differential Revision: https://reviews.llvm.org/D67185
* Test commit - add clarification to README regarding Darwin.Kit Barton2019-10-221-0/+3
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* [AMDGPU] Allow tied operand subreg foldingStanislav Mekhanoshin2019-10-221-12/+0
| | | | | | Turns out it makes sense, contrarily to what comment said. Differential Revision: https://reviews.llvm.org/D69287
* [MIPS GlobalISel] Select MSA vector generic and builtin addPetar Avramovic2019-10-222-2/+64
| | | | | | | | | | | | | | | Select vector G_ADD for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_addv_<format> will be transformed into G_ADD in legalizeIntrinsic and selected in the same way. __builtin_msa_addvi_<format> will be directly selected into ADDVI_<format> in legalizeIntrinsic. MIR tests for it have unnecessary additional copies. Capture current state of tests with run-pass=legalizer with a test in test/CodeGen/MIR/Mips. Differential Revision: https://reviews.llvm.org/D68984 llvm-svn: 375501
* [PowerPC] Turn on CR-Logical reducer passNemanja Ivanovic2019-10-222-5/+6
| | | | | | | | | | | | | | This re-commits r375152 which was pulled in r375233 because it broke the EXPENSIVE_CHECKS bot on Windows. The reason for the failure was a bug in the pass that the commit turned on by default. This patch fixes that bug and turns the pass back on. This patch has been verified on the buildbot that originally failed thanks to Simon Pilgrim. Differential revision: https://reviews.llvm.org/D52431 llvm-svn: 375497
* [Alignment][NFC] Attributes use Align/MaybeAlignGuillaume Chatelet2019-10-221-10/+8
| | | | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: jholewinski, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69278 llvm-svn: 375495
* [X86][BMI] Pull out schedule classes from bmi_andn<> and bmi_bls<>Simon Pilgrim2019-10-212-14/+15
| | | | | | Stop hardwiring classes llvm-svn: 375470
* [X86][SSE] Add OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1))) -> MOVMSK+CMP ↵Simon Pilgrim2019-10-211-0/+18
| | | | | | reduction combine llvm-svn: 375463
* AMDGPU/GlobalISel: Legalize fast unsafe FDIVAustin Kerbow2019-10-212-6/+90
| | | | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69231 llvm-svn: 375460
* AMDGPU: Select basic interp directly from intrinsicsMatt Arsenault2019-10-215-57/+29
| | | | llvm-svn: 375457
* [GISel][CombinerHelper] Add a combine turning shuffle_vector into concat_vectorsQuentin Colombet2019-10-211-0/+2
| | | | | | | | | | Teach the CombinerHelper how to turn shuffle_vectors, that concatenate vectors, into concat_vectors and add this combine to the AArch64 pre-legalizer combiner. Differential Revision: https://reviews.llvm.org/D69149 llvm-svn: 375452
* AMDGPU: Use CopyToReg for interp intrinsic loweringMatt Arsenault2019-10-211-16/+17
| | | | | | | This doesn't use the default value, so doesn't benefit from the hack to help optimize it. llvm-svn: 375450
* AMDGPU: Erase redundant redefs of m0 in SIFoldOperandsMatt Arsenault2019-10-211-0/+21
| | | | | | | | | | | | | Only handle simple inter-block redefs of m0 to the same value. This avoids interference from redefs of m0 in SILoadStoreOptimzer. I was initially teaching that pass to ignore redefs of m0, but having them not exist beforehand is much simpler. This is in preparation for deleting the current special m0 handling in SIFixSGPRCopies to allow the register coalescer to handle the difficult cases. llvm-svn: 375449
* AMDGPU: Stop adding m0 implicit def to SGPR spillsMatt Arsenault2019-10-211-13/+2
| | | | | | | | r375293 removed the SGPR spilling with scalar stores path, so this is no longer necessary. This also always had the defect of adding the def even when this path wasn't in use. llvm-svn: 375448
* AMDGPU: Slightly restructure m0 init codeMatt Arsenault2019-10-211-13/+15
| | | | | | | This will allow using another operation to produce the glue in a future change. llvm-svn: 375447
* [AMDGPU] Select AGPR in PHI operand legalizationStanislav Mekhanoshin2019-10-211-0/+4
| | | | | | | | | | | | | | If a PHI defines AGPR legalize its operands to AGPR. At the moment we can get an AGPR PHI with VGPR operands. I am not aware of any problems as it seems to be handled gracefully in RA, but this is not right anyway. It also slightly decreases VGPR pressure in some cases because we do not have to a copy via VGPR. Differential Revision: https://reviews.llvm.org/D69206 llvm-svn: 375446
* [X86] Rename matchBitOpReduction to matchScalarReduction. NFCI.Simon Pilgrim2019-10-211-4/+4
| | | | | | This doesn't need to be just for bitops, but the ops do need to be fully associative. llvm-svn: 375445
* Reverted r375425 as it broke some buildbots.Sander de Smalen2019-10-214-65/+4
| | | | llvm-svn: 375444
* SystemZISelLowering - supportedAddressingMode - silence static analyzer ↵Simon Pilgrim2019-10-211-1/+1
| | | | | | | | dyn_cast<> null dereference warning. NFCI. The static analyzer is warning about a potential null dereference, but we should be able to use cast<> directly and if not assert will fire for us. llvm-svn: 375430
* [AArch64][DebugInfo] Do not recompute CalleeSavedStackSize (Take 2)Sander de Smalen2019-10-214-4/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit message from D66935: This patch fixes a bug exposed by D65653 where a subsequent invocation of `determineCalleeSaves` ends up with a different size for the callee save area, leading to different frame-offsets in debug information. In the invocation by PEI, `determineCalleeSaves` tries to determine whether it needs to spill an extra callee-saved register to get an emergency spill slot. To do this, it calls 'estimateStackSize' and manually adds the size of the callee-saves to this. PEI then allocates the spill objects for the callee saves and the remaining frame layout is calculated accordingly. A second invocation in LiveDebugValues causes estimateStackSize to return the size of the stack frame including the callee-saves. Given that the size of the callee-saves is added to this, these callee-saves are counted twice, which leads `determineCalleeSaves` to believe the stack has become big enough to require spilling an extra callee-save as emergency spillslot. It then updates CalleeSavedStackSize with a larger value. Since CalleeSavedStackSize is used in the calculation of the frame offset in getFrameIndexReference, this leads to incorrect offsets for variables/locals when this information is recalculated after PEI. This patch fixes the lldb unit tests in `functionalities/thread/concurrent_events/*` Changes after D66935: Ensures AArch64FunctionInfo::getCalleeSavedStackSize does not return the uninitialized CalleeSavedStackSize when running `llc` on a specific pass where the MIR code has already been expected to have gone through PEI. Instead, getCalleeSavedStackSize (when passed the MachineFrameInfo) will try to recalculate the CalleeSavedStackSize from the CalleeSavedInfo. In debug mode, the compiler will assert the recalculated size equals the cached size as calculated through a call to determineCalleeSaves. This fixes two tests: test/DebugInfo/AArch64/asan-stack-vars.mir test/DebugInfo/AArch64/compiler-gen-bbs-livedebugvalues.mir that otherwise fail when compiled using msan. Reviewed By: omjavaid, efriedma Tags: #llvm Differential Revision: https://reviews.llvm.org/D68783 llvm-svn: 375425
* [NFC] Cleanup with variable name IsPPC64 & IsDarwinXiangling Liao2019-10-211-20/+18
| | | | | | | | Clean up PPCAsmPrinter with IsPPC64 and IsDarwin. Differential Revision: https://reviews.llvm.org/D69259 llvm-svn: 375420
* [ARM] Extra qdadd patternsDavid Green2019-10-212-0/+8
| | | | | | | | | This adds some new qdadd patterns to go along with the other recently added qadd's. Differential Revision: https://reviews.llvm.org/D68999 llvm-svn: 375414
* [ARM] Add qadd lowering from a sadd_satDavid Green2019-10-214-4/+19
| | | | | | | | | | | | This lowers a sadd_sat to a qadd by treating it as legal. Also adds qsub at the same time. The qadd instruction sets the q flag, but we already have many cases where we do not model this in llvm. Differential Revision: https://reviews.llvm.org/D68976 llvm-svn: 375411
* [Alignment][NFC] TargetCallingConv::setOrigAlign and ↵Guillaume Chatelet2019-10-216-21/+17
| | | | | | | | | | | | | | | | | | | TargetLowering::getABIAlignmentForCallingConv Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: sdardis, hiraditya, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69243 llvm-svn: 375407
* [ARM] Lower sadd_sat to qadd8 and qadd16David Green2019-10-214-1/+87
| | | | | | | | | | | | | | Lower the target independent signed saturating intrinsics to qadd8 and qadd16. This custom lowers them from a sadd_sat, catching the node early before it is promoted. It also adds a QADD8b and QADD16b node to mean the bottom "lane" of a qadd8/qadd16, so that we can call demand bits on it to show that it does not use the upper bits. Also handles QSUB8 and QSUB16. Differential Revision: https://reviews.llvm.org/D68974 llvm-svn: 375402
* Use Align for TFL::TransientStackAlignmentGuillaume Chatelet2019-10-2112-13/+13
| | | | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: arsenm, dschuff, jyknight, sdardis, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, fedor.sergeev, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69216 llvm-svn: 375398
* [BPF] fix indirect call assembly codeYonghong Song2019-10-211-1/+1
| | | | | | | | | | | | | Currently, for indirect call, the assembly code printed out as callx <imm> This is not right, it should be callx <reg> Fixed the issue with proper format. Differential Revision: https://reviews.llvm.org/D69229 llvm-svn: 375386
* [X86] Check Subtarget.hasSSE3() before calling shouldUseHorizontalOp and ↵Craig Topper2019-10-201-1/+1
| | | | | | | | | | emitting X86ISD::FHADD in LowerUINT_TO_FP_i64. This was a regression from r375341. Fixes PR43729. llvm-svn: 375381
* Fix buildbot error in SIRegisterInfo.cpp.Zinovy Nis2019-10-201-3/+4
| | | | llvm-svn: 375373
* AMDGPU: Increase vcc liveness scan thresholdMatt Arsenault2019-10-201-2/+4
| | | | | | | Avoids a test regression in a future patch. Also add debug printing on this case, so I waste less time debugging folds in the future. llvm-svn: 375367
* AMDGPU: Split flat offsets that don't fit in DAGMatt Arsenault2019-10-203-3/+96
| | | | | | | | | | We handle it this way for some other address spaces. Since r349196, SILoadStoreOptimizer has been trying to do this. This is after SIFoldOperands runs, which can change the addressing patterns. It's simpler to just split this earlier. llvm-svn: 375366
* AMDGPU: Fix missing OPERAND_IMMEDIATEMatt Arsenault2019-10-201-12/+13
| | | | llvm-svn: 375365
* AMDGPU: Don't re-get the subtargetMatt Arsenault2019-10-201-21/+9
| | | | | | It's already available in the class. llvm-svn: 375363
* AMDGPU: Don't error on calls to null or undefMatt Arsenault2019-10-201-0/+9
| | | | | | Calls to constants should probably be generally handled. llvm-svn: 375356
* [X86] Pulled out helper to decode target shuffle element sentinel values to ↵Simon Pilgrim2019-10-191-13/+22
| | | | | | | | 'Zeroable' known undef/zero bits. NFCI. Renamed 'resolveTargetShuffleAndZeroables' to 'resolveTargetShuffleFromZeroables' to match. llvm-svn: 375348
* [TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold ↵Sanjay Patel2019-10-192-0/+5
| | | | | | | | | | | | | | | | | (1/2) Provides a TLI hook to allow targets to relax the emission of shifts, thus enabling codegen improvements on targets with no multiple shift instructions and cheap selects or branches. Contributes to a Fix for PR43559: https://bugs.llvm.org/show_bug.cgi?id=43559 Patch by: @joanlluch (Joan LLuch) Differential Revision: https://reviews.llvm.org/D69116 llvm-svn: 375347
* [X86][SSE] lowerV16I8Shuffle - tryToWidenViaDuplication - undef unpack argsSimon Pilgrim2019-10-191-1/+9
| | | | | | tryToWidenViaDuplication lowers using the shuffle_v8i16(unpack_v16i8(shuffle_v8i16(x),shuffle_v8i16(x))) pattern, but the unpack only needs the even/odd 16i8 args if the original v16i8 shuffle mask references the even/odd elements - which isn't true for many extension style shuffles. llvm-svn: 375342
* [X86][SSE] LowerUINT_TO_FP_i64 - only use HADDPD for size/fast-hopsSimon Pilgrim2019-10-191-12/+11
| | | | | | | | We were always generating a single source HADDPD, but really we should only do this if shouldUseHorizontalOp says its a good idea. Differential Revision: https://reviews.llvm.org/D69175 llvm-svn: 375341
* Prune a LegacyDivergenceAnalysis and MachineLoopInfo include eachReid Kleckner2019-10-1916-3/+20
| | | | | | Now X86ISelLowering doesn't depend on many IR analyses. llvm-svn: 375320
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