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* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-173-11/+54
| | | | | | | | | | the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 llvm-svn: 157019
* Remove incorrect pattern for ARM SMML instruction.Tim Northover2012-05-171-2/+1
| | | | | | Patch by Meador Inge. llvm-svn: 156989
* This patch adds the register class for MIPS16 as well as the ability forAkira Hatanaka2012-05-165-11/+26
| | | | | | | | | | | | | | | llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. llvm-svn: 156958
* Hexagon: Remove unused command line option.Benjamin Kramer2012-05-161-2/+0
| | | | llvm-svn: 156917
* Avoid creating a cycle when folding load / op with flag / store. PR11451474. ↵Evan Cheng2012-05-161-0/+14
| | | | | | rdar://11451474 llvm-svn: 156896
* Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach2012-05-1510-0/+16
| | | | | | | | Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
* Temporarily disable anti-dependence breaking for Mips until bug 12829 isAkira Hatanaka2012-05-151-1/+1
| | | | | | resolved. llvm-svn: 156801
* Remove extraneous ';'.Bill Wendling2012-05-151-1/+1
| | | | llvm-svn: 156791
* Add a command line option to skip the delay slot filler pass entirely for Mips.Akira Hatanaka2012-05-141-0/+10
| | | | | | | | | | The purpose of this option is to silence error messages issued by machine verifier passes and enable them to run to the end. If this option is not provided, -verify-machineinstrs complains when it discovers there is a non-terminator instruction (an instruction that is in a delay slot) after the first terminator in a basic block. llvm-svn: 156790
* Fix use of uninitialized variable.David Blaikie2012-05-141-1/+1
| | | | | | Found by GCC's maybe-uninitialized. llvm-svn: 156780
* Revert 156634 upon request until code improvement changes are made.Brendon Cahoon2012-05-1415-3689/+339
| | | | llvm-svn: 156775
* Rename @llvm.debugger to @llvm.debugtrap.Dan Gohman2012-05-141-1/+1
| | | | llvm-svn: 156774
* Hexagon: Initialize TBB to 0.Benjamin Kramer2012-05-131-0/+1
| | | | | | Found by valgrind. llvm-svn: 156744
* Make sure new value jump is enabled for Hexagon V5 as well.Sirish Pande2012-05-121-10/+27
| | | | llvm-svn: 156700
* Support for Hexagon feature, New Value Jump.Sirish Pande2012-05-127-2/+682
| | | | llvm-svn: 156698
* Remove MipsEmitGPRestore.cpp.Akira Hatanaka2012-05-123-99/+0
| | | | llvm-svn: 156696
* Delete all functions that are no longer needed in MipsFunctionInfo, includingAkira Hatanaka2012-05-122-15/+1
| | | | | | | | | the ones that get or set the frame index for the $gp save slot. Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns GP. This function should always return a virtual register. llvm-svn: 156695
* Stop reserving register $gp. Do not call isGPFI to check whether a frame objectAkira Hatanaka2012-05-121-8/+1
| | | | | | is the $gp save slot. llvm-svn: 156694
* Do not add the pass which restores $gp after every function call.Akira Hatanaka2012-05-121-9/+0
| | | | llvm-svn: 156693
* Make the following changes in MipsISelLowering.cpp:Akira Hatanaka2012-05-121-8/+8
| | | | | | | | | - Stop creating stack frame objects needed for saving $gp. - Insert a node that copies the global pointer register to register $gp before the call node. This will ensure $gp is valid at the entry of the called function. llvm-svn: 156692
* Make the following changes in MipsFrameLowering.cpp:Akira Hatanaka2012-05-121-32/+3
| | | | | | | | - Stop emitting instructions needed to initialize the global pointer register. - Stop emitting .cprestore directive. - Do not take into account the $gp save slot when computing stack size. llvm-svn: 156691
* Make the following changes in MipsAsmPrinter.cpp:Akira Hatanaka2012-05-123-31/+11
| | | | | | | | | - Remove code which lowers pseudo SETGP01. - Fix LowerSETGP01. The first two of the three instructions that are emitted to initialize the global pointer register now use register $2. - Stop emitting .cpload directive. llvm-svn: 156689
* Insert instructions to the entry basic block which initializes the globalAkira Hatanaka2012-05-121-35/+52
| | | | | | | | | | | | | | | | | | pointer register. This is the first of the series of patches which clean up the way global pointer register is used. The patches will make the following improvements: - Make $gp an allocatable temporary register rather than reserving it. - Use a virtual register as the global pointer register and let the register allocator decide which register to assign to it or whether spill/reloads are needed. - Make sure $gp is valid at the entry of a called function, which is necessary for functions using lazy binding. - Remove the need for emitting .cprestore and .cpload directives. llvm-svn: 156671
* Do not replace operands of pseudo instructions with register $zero.Akira Hatanaka2012-05-111-1/+2
| | | | llvm-svn: 156663
* [fast-isel] Add support for selecting @llvm.trap().Chad Rosier2012-05-111-0/+4
| | | | llvm-svn: 156646
* Updated instruction table due to addded intrinsics.Brendon Cahoon2012-05-111-1880/+1943
| | | | llvm-svn: 156644
* Remove warnings from HexagonVLIWPacketizer.Sirish Pande2012-05-111-3/+3
| | | | llvm-svn: 156636
* Hexagon constant extender support.Brendon Cahoon2012-05-1115-339/+3626
| | | | | | Patch by Jyotsna Verma. llvm-svn: 156634
* Typo.Chad Rosier2012-05-111-1/+1
| | | | llvm-svn: 156633
* [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. ↵Chad Rosier2012-05-111-12/+2
| | | | | | Minor cleanup. llvm-svn: 156632
* Hexagon V5 intrinsics support.Sirish Pande2012-05-113-615/+1061
| | | | llvm-svn: 156631
* [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-regChad Rosier2012-05-111-4/+21
| | | | | | | | retval. Hoists check before emitting the call to avoid unnecessary work. rdar://11430407 PR12796 llvm-svn: 156628
* [fast-isel] Rather then assert (or segfault in a non-asserts build), fall backChad Rosier2012-05-111-2/+4
| | | | | | | | to selection DAG isel if we're unable to handle a non-double multi-reg retval. rdar://11430407 PR12796 llvm-svn: 156622
* The return type is an unsigned, not a bool.Chad Rosier2012-05-111-1/+1
| | | | llvm-svn: 156621
* Add space before an open parenthesis in control flow statements.Manman Ren2012-05-111-2/+2
| | | | llvm-svn: 156620
* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-114-130/+350
| | | | llvm-svn: 156615
* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-114-16/+35
| | | | | | | This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong code here (see the update to test/CodeGen/X86/tls-pie.ll). llvm-svn: 156611
* Added the missing bit definition for the 4th bit of the STR (post reg) ↵Silviu Baranga2012-05-112-0/+5
| | | | | | instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-112-3/+9
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
* Fix a misleading comment.Akira Hatanaka2012-05-111-1/+1
| | | | llvm-svn: 156603
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-111-27/+119
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-111-0/+3
| | | | | | but it generates int3 on x86 instead of ud2. llvm-svn: 156593
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-103-223/+426
| | | | llvm-svn: 156579
* Add support for the 'X' inline asm operand modifier.Eric Christopher2012-05-101-4/+16
| | | | | | Patch by Jack Carter. llvm-svn: 156577
* Hexagon V5 Support - V5 td file.Sirish Pande2012-05-101-0/+626
| | | | llvm-svn: 156569
* Hexagon V5 FP Support.Sirish Pande2012-05-1014-194/+519
| | | | llvm-svn: 156568
* Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren2012-05-101-118/+27
| | | | | | This commit broke an external linux bot and gave a compile-time warning. llvm-svn: 156556
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-101-27/+118
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156550
* Fix merge-typo and cleanupNadav Rotem2012-05-101-5/+3
| | | | llvm-svn: 156541
* AVX2: Add an additional broadcast idiom.Nadav Rotem2012-05-101-2/+5
| | | | llvm-svn: 156540
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