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* [mips] Materialize constants for multiplicationSimon Dardis2018-04-131-3/+76
| | | | | | | | | | | | | | | | | | | | | | | Previously, the MIPS backend would alwyas break down constant multiplications into a series of shifts, adds, and subs. This patch changes that so the cost of doing so is estimated. The cost is estimated against worst case constant materialization and retrieving the results from the HI/LO registers. For cases where the value type of the multiplication is not legal, the cost of legalization is estimated and is accounted for before performing the optimization of breaking down the constant This resolves PR36884. Thanks to npl for reporting the issue! Reviewers: abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D45316 llvm-svn: 330037
* [X86] Remove remaining itinerary support from instructions and target (PR37093)Simon Pilgrim2018-04-133-13/+0
| | | | llvm-svn: 330035
* [ARM] FP16 vmaxnm/vminnm scalar instructionsSjoerd Meijer2018-04-133-2/+20
| | | | | | | | | This adds code generation support for the FP16 vmaxnm/vminnm scalar instructions. Differential Revision: https://reviews.llvm.org/D44675 llvm-svn: 330034
* [ARC] Add LImm support for J/JLYan Luo2018-04-131-5/+17
| | | | llvm-svn: 330031
* [X86] Generalize X86FixupLEAs to work with TargetSchedModelSimon Pilgrim2018-04-131-3/+4
| | | | | | Similar to rL329834, don't rely on itinerary scheduler model to determine latencies for LEA thresholds, use the generic TargetSchedModel::computeInstrLatency call. llvm-svn: 330030
* Remove comment reference to itineraries. NFCI.Simon Pilgrim2018-04-131-1/+1
| | | | llvm-svn: 330025
* [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructionsSander de Smalen2018-04-133-0/+64
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45618 llvm-svn: 330024
* [X86][AVX512] UNPCKL/H PS and PD should be scheduled with WriteFShuffle not ↵Simon Pilgrim2018-04-131-2/+2
| | | | | | WriteFAdd llvm-svn: 330023
* [X86] Remove remaining OpndItins/SizeItins from all instruction defs (PR37093)Simon Pilgrim2018-04-132-1715/+1301
| | | | llvm-svn: 330022
* Remove comment references to itineraries. NFCI.Simon Pilgrim2018-04-133-4/+4
| | | | llvm-svn: 330021
* Remove out of data comment. NFCI.Simon Pilgrim2018-04-131-2/+1
| | | | llvm-svn: 330019
* [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.Sander de Smalen2018-04-133-1/+107
| | | | | | | | | | | | | | | | | | | | Summary: Added instructions for contiguous stores, ST1, with scalar+imm addressing modes and corresponding tests. The patch also adds parsing of 'mul vl' as needed for the VL-scaled immediate. This is patch [6/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45432 llvm-svn: 330014
* [X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093)Simon Pilgrim2018-04-132-622/+566
| | | | llvm-svn: 330013
* [NEON] Support intrinsic for scalar and vector versions of the VRINTN ↵Ivan A. Kosarev2018-04-131-1/+1
| | | | | | | | instruction Differential Revision: https://reviews.llvm.org/D45514 llvm-svn: 330011
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-04-134-4/+4
| | | | | | "the the" -> "the", "we we" -> "we", etc llvm-svn: 330006
* [AArch64][SVE] Asm: Add support for parsing and printing SVE vector lists.Sander de Smalen2018-04-133-2/+78
| | | | | | | | | | | | | | | | | | | Summary: Added Z_(b|h|s|d) vector list RegisterOperands along with support to add/print the vector lists. This is patch [5/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: fhahn Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45431 llvm-svn: 330000
* [X86] Introduce cldemote instructionGabor Buella2018-04-134-0/+11
| | | | | | | | | | | | | | Hint to hardware to move the cache line containing the address to a more distant level of the cache without writing back to memory. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45256 llvm-svn: 329992
* [X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.Craig Topper2018-04-131-18/+0
| | | | | | | | This completes the work started in r329604 and r329605 when we changed clang to no longer use the intrinsics. We lost some InstCombine SimplifyDemandedBit optimizations through this change as we aren't able to fold 'and', bitcast, shuffle very well. llvm-svn: 329990
* [X86] Remove unused MoveLoadStoreItins/ShiftOpndItins schedule class wrappers.Simon Pilgrim2018-04-122-36/+14
| | | | | | Was being used to move around empty/unused itineraries... llvm-svn: 329970
* [X86] Remove x86 InstrItinClass entries (PR37093)Simon Pilgrim2018-04-123-241/+94
| | | | | | This removes the last of the x86 schedule itineraries, I'm intending to cleanup the remaining uses of NoItinerary/OpndItins/etc. before resolving PR37093. llvm-svn: 329967
* AArch64: Introduce a DAG combine for folding offsets into addresses.Peter Collingbourne2018-04-122-15/+68
| | | | | | | | | | | This is a code size win in code that takes offseted addresses frequently, such as C++ constructors that typically need to compute an offseted address of a vtable. This reduces the size of Chromium for Android's .text section by 108KB. Differential Revision: https://reviews.llvm.org/D45199 llvm-svn: 329956
* [X86] Remove InstrItinClass entries from all x86 instruction defs (PR37093)Simon Pilgrim2018-04-123-318/+284
| | | | llvm-svn: 329953
* [X86] Remove InstrItinClass entries from SSE/AVX instructions defs (PR37093)Simon Pilgrim2018-04-122-521/+498
| | | | llvm-svn: 329945
* [X86] Remove explicit SSE/AVX schedule itineraries from defs (PR37093)Simon Pilgrim2018-04-123-526/+463
| | | | llvm-svn: 329940
* [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0Sameer AbuAsal2018-04-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GCC compresses the pseudo instruction "mv rd, rs", which is an alias of "addi rd, rs, 0", to "c.mv rd, rs". In LLVM we rely on the canonical MC instruction (MCInst) to do our compression checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv rd, rs" we lose this compression opportunity to gcc. In this patch we fix that by adding an addi to c.mv compression pattern, the instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like gcc does. Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal). Reviewers: asb, apazos, zzheng, mgrang, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, llvm-commits Differential Revision: https://reviews.llvm.org/D45583 llvm-svn: 329939
* [X86] Remove remaining gpr schedule itineraries (PR37093)Simon Pilgrim2018-04-124-353/+226
| | | | llvm-svn: 329938
* [X86] Introduce LLVM wbinvd intrinsicGabor Buella2018-04-121-1/+1
| | | | | | | | | | | | A previously missing intrinsic for an old instruction. Reviewers: craig.topper, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45312 llvm-svn: 329936
* [X86] Remove gpr shift/extension schedule itineraries (PR37093)Simon Pilgrim2018-04-123-343/+270
| | | | llvm-svn: 329933
* [Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-PrecisionLei Huang2018-04-122-1/+22
| | | | | | | | | | | Legalize and emit code for: * xscvsdqp * xscvudqp Differential Revision: https://reviews.llvm.org/D45230 llvm-svn: 329931
* [MIPS GlobalISel] remove superfluous #includes (NFC)Petar Jovanovic2018-04-125-14/+1
| | | | | | | Remove superfluous #includes. Minor code style change in MipsCallLowering::lowerFormalArguments(). llvm-svn: 329926
* [AArch64] Move AFI->setRedZone(false) to top of emitPrologueJessica Paquette2018-04-121-1/+5
| | | | | | | | | | | | | AFI->setRedZone(false) was put in the wrong place before, and so it only fired on functions that didn't have stack frames. This moves that to the top of emitPrologue to make sure that every function without a redzone has it set correctly. This also adds a function representing one of the early exit cases (GHC calling convention) to the MachineOutliner noredzone test to ensure that we can outline from functions like these, where we never use a redzone. llvm-svn: 329922
* [mips] Correct the predicates of the load/store (double)word for coprocessor 3.Simon Dardis2018-04-121-4/+6
| | | | llvm-svn: 329913
* [X86] Remove AES/CLMUL/CRC32/LDDQU/MOVNT/POPCNT/SHA schedule itineraries ↵Simon Pilgrim2018-04-124-100/+70
| | | | | | (PR37093) llvm-svn: 329912
* [AArch64][AsmParser] Unify 'addVectorListOperands' functions.Sander de Smalen2018-04-122-38/+34
| | | | | | | | | | | | | | | | | | | | Summary: Merged 'addVectorList64Operands' and 'addVectorList128Operands' into a generic 'addVectorListOperands', which can be easily extended to work for SVE vectors. This is patch [4/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45430 llvm-svn: 329909
* [X86] Remove remaining system/special schedule itineraries (PR37093)Simon Pilgrim2018-04-125-540/+381
| | | | llvm-svn: 329906
* [mips] Correct the predicates for special nops, tlb ctrl instrs, software ↵Simon Dardis2018-04-122-25/+34
| | | | | | | | | | breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
* [X86] Remove system/control schedule itineraries (PR37093)Simon Pilgrim2018-04-128-527/+356
| | | | llvm-svn: 329903
* [AArch64][AsmParser] Make parse function for VectorLists generic to other ↵Sander de Smalen2018-04-122-74/+100
| | | | | | | | | | | | | | | | | | | | | | | | vector types. Summary: Added 'RegisterKind' to the VectorListOp structure, so that this operand type can be reused for SVE vector lists in a later patch. It also refactors the 'tryParseVectorList' function so it can be used directly in the ParserMethod of an operand. The parsing can now parse multiple kinds of vectors and recover if there is no match. This is patch [3/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45429 llvm-svn: 329900
* [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVCShiva Chen2018-04-121-2/+3
| | | | | | | | | | | | | | | | | | Summary: According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only allow 32-bit instruction alignment, but instruction allow to be aligned to 16-bit boundaries for C-extension. So we just align to 4 bytes and 2 bytes for C-extension is enough. Reviewers: asb, apazos Differential Revision: https://reviews.llvm.org/D45560 Patch by Kito Cheng. llvm-svn: 329899
* [X86] Remove CMOV/SETCC schedule itineraries (PR37093)Simon Pilgrim2018-04-122-26/+13
| | | | llvm-svn: 329898
* [X86] Remove MMX/3DNow schedule itineraries (PR37093)Simon Pilgrim2018-04-124-387/+226
| | | | llvm-svn: 329896
* [X86] Remove X87 schedule itineraries (PR37093)Simon Pilgrim2018-04-123-172/+101
| | | | | | First of a number of commits to remove x86 schedule itineraries entirely - approved off-line with @craig.topper llvm-svn: 329893
* [SystemZ] Use ResourceCycles=30 for FPd unit (NFC).Jonas Paulsson2018-04-122-22/+4
| | | | | | | This is better than listing FPd 30 times :-) Review: Ulrich Weigand llvm-svn: 329887
* [SystemZ] Remove FullInstRWOverlapCheck from SchedMachineModels.Jonas Paulsson2018-04-124-18/+10
| | | | | | | | This is NFC, even though it caught just a few cases of overlapping regular expressions. Review: Ulrich Weigand llvm-svn: 329886
* [HexagonMachineScheduler] Remove local (copied) getWeakLeft().Jonas Paulsson2018-04-121-4/+0
| | | | | | | Since the common code getWeakLeft() is now available, there should not be a local copy of this function in target. llvm-svn: 329885
* [MachineScheduler] NFC refactoringJonas Paulsson2018-04-121-26/+32
| | | | | | | | | | | | | | | | This patch makes tryCandidate() virtual and some utility functions like tryLess(), tryGreater(), ... externally available (used to be static). This makes it possible for a target to derive a new MachineSchedStrategy from GenericScheduler and reuse most parts. It was necessary to wrap functions with the same names in AMDGPU/SIMachineScheduler in a local namespace. Review: Andy Trick, Florian Hahn https://reviews.llvm.org/D43329 llvm-svn: 329884
* [RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury2018-04-123-11/+37
| | | | | | | | Also add double-prevoius-failure.ll which captures a test case that at one point triggered a compiler crash, while developing calling convention support for f64 on RV32D with soft-float ABI. llvm-svn: 329877
* [RISCV] Codegen support for RV32D floating point conversion operationsAlex Bradbury2018-04-122-0/+15
| | | | | | | This also includes support and a test for truncating stores, which are now possible thanks to the fpround pattern. llvm-svn: 329876
* [RISCV] Add codegen support for RV32D floating point arithmetic operationsAlex Bradbury2018-04-122-1/+33
| | | | llvm-svn: 329874
* [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ↵Alex Bradbury2018-04-126-22/+327
| | | | | | | | | | | | | | | | conv fadd.d is required in order to force floating point registers to be used in test code, as parameters are passed in integer registers in the soft float ABI. Much of this patch is concerned with support for passing f64 on RV32D with a soft-float ABI. Similar to Mips, introduce pseudoinstructions to build an f64 out of a pair of i32 and to split an f64 to a pair of i32. BUILD_PAIR and EXTRACT_ELEMENT can't be used, as a BITCAST to i64 would be necessary, but i64 is not a legal type. llvm-svn: 329871
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