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* [X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper2017-10-214-118/+44
| | | | | | | | | | | | the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
* Fix MSVC 'result of 32-bit shift implicitly converted to 64 bits' warning. NFCI.Simon Pilgrim2017-10-211-2/+2
| | | | llvm-svn: 316271
* [PPC CodeGen] Fix the bitreverse.i64 intrinsic.Fangrui Song2017-10-211-6/+8
| | | | | | | | | | Summary: The two 32-bit words were swapped. Subscribers: nemanjai, kbarton Differential Revision: https://reviews.llvm.org/D38705 llvm-svn: 316270
* [X86] Do not generate __multi3 for mul i128 on X86Craig Topper2017-10-211-0/+1
| | | | | | | | | | | | | | | | Summary: __multi3 is not available on x86 (32-bit). Setting lib call name for MULI_128 to nullptr forces DAGTypeLegalizer::ExpandIntRes_MUL to generate instructions for 128-bit multiply instead of a call to an undefined function. This fixes PR20871 though it may be worth looking at why licm and indvars combine to generate 65-bit multiplies in that test. Patch by Riyaz V Puthiyapurayil Reviewers: craig.topper, schweitz Reviewed By: craig.topper, schweitz Subscribers: RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D38668 llvm-svn: 316254
* [Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek2017-10-201-1/+1
| | | | llvm-svn: 316243
* [WebAssembly] MC: Fix crash when -g specified.Sam Clegg2017-10-201-4/+4
| | | | | | | | | At this point we don't output any debug sections or thier relocations. Differential Revision: https://reviews.llvm.org/D39076 llvm-svn: 316240
* [globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders2017-10-201-14/+14
| | | | | | | ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. llvm-svn: 316237
* [Hexagon] Report error instead of crashing on wrong inline-asm constraintsKrzysztof Parzyszek2017-10-201-13/+14
| | | | llvm-svn: 316236
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-2010-2623/+2244
| | | | llvm-svn: 316228
* [X86][SSE] getTargetShuffleMask - check shuffle input value types. NFCI.Simon Pilgrim2017-10-201-0/+46
| | | | | | To help identify shuffle combine issues llvm-svn: 316222
* Make x86 __ehhandler comdat if parent function isDave Lee2017-10-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change comes from using lld for i686-windows-msvc. Before this change, lld emits an error of: error: relocation against symbol in discarded section: .xdata It's possible that this could be addressed in lld, but I think this change is reasonable on its own. At a high level, this is being generated: A (.text comdat) -> B (.text) -> C (.xdata comdat) Where A is a C++ inline function, which references B, an exception handler thunk, which references C, the exception handling info. With this structure, lld will error when applying relocations to B if the C it references has been discarded (some other C has been selected). This change checks if A is comdat, and if so places the exception registration thunk (B) in the comdata group of A (and B). It appears that MSVC makes the __ehhandler function comdat. Is it possible that duplicate thunks are being emitted into the final binary with other linkers, or are they stripping the unused thunks? Reviewers: rnk, majnemer, compnerd, smeenai Reviewed By: rnk, compnerd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38940 llvm-svn: 316219
* [Hexagon] Allow redefinition with immediates for hw loop conversionKrzysztof Parzyszek2017-10-202-7/+13
| | | | | | | | | | | Normally, if the registers holding the induction variable's bounds are redefined inside of the loop's body, the loop cannot be converted to a hardware loop. However, if the redefining instruction is actually loading an immediate value into the register, this conversion is both possible and legal (since the immediate itself will be used in the loop setup in the preheader). llvm-svn: 316218
* Revert "[mips] Reordering callseq* nodes to be linear"Aleksandar Beserminji2017-10-202-27/+26
| | | | | | | This reverts commit r314507, because the original patch is causing test failures. llvm-svn: 316215
* [ARM] Use post-RA MI scheduler when +use-misched is setEugene Leviant2017-10-201-1/+8
| | | | | | Differential revision: https://reviews.llvm.org/D39100 llvm-svn: 316214
* Disabling the transformation introduced in r315888Nemanja Ivanovic2017-10-201-2/+2
| | | | | | | The commit at https://reviews.llvm.org/rL315888 is causing some failures with internal testing. Disabling this code until we can resolve the issues. llvm-svn: 316199
* [RISCV] Add missing hunk from r316188Alex Bradbury2017-10-191-1/+3
| | | | | | r316188 didn't set guessInstructionProperties=1 as it should have done. llvm-svn: 316189
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-1922-11/+938
| | | | | | | | | | | | | This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
* [X86] Remove LowerEXTRACT_SUBVECTOR handler. All EXTRACT_SUBVECTORs are ↵Craig Topper2017-10-191-26/+0
| | | | | | marked as legal. llvm-svn: 316182
* The cost of splitting a large vector instruction is not being taken into ↵Graham Yiu2017-10-192-0/+13
| | | | | | | | | | account by the getUserCost function. This was leading to some loops being over unrolled. The cost of a vector instruction is now being multiplied by the cost of the type legalization. This will return a more accurate cost. Committing on behalf on Brad Nemanich (brad.nemanich@ibm.com) Differential Revision: https://reviews.llvm.org/D38961 llvm-svn: 316174
* [Hexagon] Fix store conversion from rr to io in optimize addressing modesKrzysztof Parzyszek2017-10-191-6/+5
| | | | llvm-svn: 316170
* [RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expectedAlex Bradbury2017-10-191-0/+10
| | | | | | | This is necessary to avoid an assertion in the included test case and similar assembler inputs. llvm-svn: 316168
* [RISCV][NFC] Drop unused parameter from createImm helper in RISCVAsmParserAlex Bradbury2017-10-191-4/+3
| | | | llvm-svn: 316167
* [X86] Replace custom scalar integer absolute matching with ISD::ABS lowering.Simon Pilgrim2017-10-191-36/+21
| | | | | | | | | | | | x86 has its own copy of integer absolute pattern matching to combine directly to a SUB+CMOV. This patch removes the x86 combine and adds custom lowering support for ISD::ABS instead, allowing us to use the DAGCombiner version. Additional test cases are already covered by iabs.ll (rL315706 and rL315711). Differential Revision: https://reviews.llvm.org/D38895 llvm-svn: 316162
* [RISCV] Prepare for the use of variable-sized register classesAlex Bradbury2017-10-198-220/+276
| | | | | | | | | | While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159
* [Hexagon] New HVX target features.Sumanth Gundapaneni2017-10-187-86/+111
| | | | | | | | | | | | | | | | | | | | | | This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
* [Hexagon] Update Hexagon ArchEnum and sync some downstream changes(NFC)Sumanth Gundapaneni2017-10-186-68/+76
| | | | | | Differential Revision: https://reviews.llvm.org/D38850 llvm-svn: 316099
* [Hexagon] Mark vector loads as predicable, update instruction mappingsKrzysztof Parzyszek2017-10-182-56/+154
| | | | | | | | All loads of form V6_vL32b_{,cur,nt,tmp,nt_cur,nt_tmp}_{ai,pi,ppu} are predicable on v62 (but not on v60). Mark them all as predicable in the instruction definitions, and handle the v60 case in HII::isPredicable. llvm-svn: 316098
* AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistencyKonstantin Zhuravlyov2017-10-181-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D38957 llvm-svn: 316097
* [RISCV] Bugfix createRISCVELFObjectWriterAlex Bradbury2017-10-181-1/+1
| | | | | | | r315275 set the IsLittleEndian parameter incorrectly. This patch corrects this, and adds a test to ensure such mistakes will be caught in the future. llvm-svn: 316091
* [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM modeAndre Vieira2017-10-181-2/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D38347 llvm-svn: 316085
* [mips] Fix analyzeBranch to handle debug dataSimon Dardis2017-10-181-1/+7
| | | | | | | | | | | | | | | | | | | | | In the case where there was a conditional branch followed by a unconditional branch with debug instruction separating them, MipsInstrInfo::analyzeBranch would not skip past debug instruction when searching for the second branch which give erroneous results about the control flow of the block. This could lead to the branch folder to merge the non-fall through case into it's predecessor, leaving the conditional branch with a dangling basic block operand. This resolves PR34975. Thanks to Alexander Richardson for reporting the issue! Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39003 llvm-svn: 316084
* Untabify.NAKAMURA Takumi2017-10-183-7/+7
| | | | llvm-svn: 316079
* [AVR] Update to current LLVM APIDylan McKay2017-10-185-9/+19
| | | | | | | r315410 broke a number of things in the AVR backend, which are now fixed. llvm-svn: 316076
* [AVX512][AVX2]Cost calculation for interleave load/store patterns ↵Michael Zuckerman2017-10-181-7/+43
| | | | | | | | | | | | | | | | | | | {v8i8,v16i8,v32i8,v64i8} This patch adds accurate instructions cost. The formula presents two cases(stride 3 and stride 4) and calculates the cost according to the VF and stride. Reviewers: 1. delena 2. Farhana 3. zvi 4. dorit 5. Ayal Differential Revision: https://reviews.llvm.org/D38762 Change-Id: If4cfbd4ac0e63694e8144cb78c7fa34850647ff7 llvm-svn: 316072
* [PowerPC] Use helper functions to check sign-/zero-extended valueHiroshi Inoue2017-10-181-23/+11
| | | | | | | | | | | Helper functions to identify sign- and zero-extending machine instruction is introduced in rL315888. This patch makes PPCInstrInfo::optimizeCompareInstr use the helper functions. It simplifies the code and also makes possible more optimizations since the helper can do more analysis than the original check code; I observed about 5000 more compare instructions are eliminated while building LLVM. Also, this patch fixes a bug in helpers on ANDIo instruction handling due to the order of checks. This bug causes a failure in an existing test case for optimizeCompareInstr. Differential Revision: https://reviews.llvm.org/D38988 llvm-svn: 316071
* Fixing bug issue https://bugs.llvm.org/show_bug.cgi?id=34978Michael Zuckerman2017-10-181-0/+2
| | | | | Change-Id: I7f13d5bcb181be2860377df7b40e1579a8ad4add llvm-svn: 316067
* [aarch64][globalisel] Register banks and classes should have distinct names.Daniel Sanders2017-10-182-5/+4
| | | | | | Otherwise they are ambiguous in MIR. llvm-svn: 316047
* AMDGPU : Fix an error for the llvm.cttz implementation.Wei Ding2017-10-171-3/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D39014 llvm-svn: 316037
* AArch64: Enable AES instruction fusion on Cyclone.Matthias Braun2017-10-171-2/+5
| | | | | | | | | | | Note that cyclone itself doesn't fuse, but newer apple chips do and we are using cyclone as the default when targeting apple OSes. The current code also does not capture all fusion patterns of apple CPUs yet; I am still looking for ways to refactor the code nicely to extend it. llvm-svn: 316036
* AArch64: account for possible frame index operand in compares.Tim Northover2017-10-172-0/+9
| | | | | | | | | If the address of a local is used in a comparison, AArch64 can fold the address-calculation into the comparison via "adds". Unfortunately, a couple of places (both hit in this one test) are not ready to deal with that yet and just assume the first source operand is a register. llvm-svn: 316035
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-171-8/+15
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 316034
* AMDGPU: Start generating metadata for MaxFlatWorkGroupSizeKonstantin Zhuravlyov2017-10-171-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D38958 llvm-svn: 316024
* Fix `FaultMaps` crash when the out streamer is reusedYichao Yu2017-10-171-0/+1
| | | | | | | | | | | | | | | | | | | Summary: Make sure the map is cleared before processing a new module. Similar to what is done on `StackMaps`. This issue is similar to D38588, though this time for FaultMaps (on x86) rather than ARM/AArch64. Other than possible mixing of information between modules, the crash is caused by the pointers values in the map that was allocated by the bump pointer allocator that is unwinded when emitting the next file. This issue has been around since 3.8. This issue is likely much harder to write a test for since AFAICT it requires emitting something much more compilcated (and possibly real code) instead of just some random bytes. Reviewers: skatkov, sanjoy Reviewed By: skatkov, sanjoy Subscribers: sanjoy, aemerson, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D38924 llvm-svn: 315990
* [X86][SKL] Updated scheduling information for the SkylakeClient targetGadi Haber2017-10-171-3072/+3271
| | | | | | | | | | | | | | Updated the scheduling information for the SkylakeClient target with the following changes: 1. regrouped the instructions after adding load and store latencies. 2. regrouped the instructions after adding identified missing ports in several groups. The changes were made after revisiting the latencies impact of all the load and store uOps. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D38727 Change-Id: I778a308cc11e490e8fa5e27e2047412a1dca029f llvm-svn: 315978
* [X86] Fix typo in comment. NFCCraig Topper2017-10-171-1/+1
| | | | llvm-svn: 315969
* Use the return value of UpdateNodeOperands(); in some cases, ↵Mark Searles2017-10-161-2/+1
| | | | | | | | UpdateNodeOperands() modifies the node in-place and using the return value isn’t strictly necessary. However, it does not necessarily modify the node, but may return a resultant node if it already exists in the DAG. See comments in UpdateNodeOperands(). In that case, the return value must be used to avoid such scenarios as an infinite loop (node is assumed to have been updated, so added back to the worklist, and re-processed; however, node hasn’t changed so it is once again passed to UpdateNodeOperands(), assumed modified, added back to worklist; cycle infinitely repeats). Differential Revision: https://reviews.llvm.org/D38466 llvm-svn: 315957
* Re-apply [AArch64][RegisterBankInfo] Use the statically computed mappings ↵Quentin Colombet2017-10-161-4/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for COPY This reverts commit r315823, thus re-applying r315781. Also make sure we don't use G_BITCAST mapping for non-generic registers. Non-generic registers don't have a type but do have a reg bank. Something the COPY mapping now how to deal with but the G_BITCAST mapping don't. -- Original Commit Message -- We use to resort on the generic implementation to get the mappings for COPYs. The generic implementation resorts on table lookup and dynamically allocated objects to get the valid mappings. Given we already know how to map G_BITCAST and have the static mappings for them, use that code path for COPY as well. This is much more efficient. Improve the compile time of RegBankSelect by up to 20%. Note: When we eventually generate all the mappings via TableGen, we wouldn't have to do that dance to shave compile time. The intent of this change was to make sure that moving to static structure really pays off. NFC. llvm-svn: 315947
* [AArch64][RegisterBankInfo] Add mapping support for G_BITCAST of s128Quentin Colombet2017-10-161-2/+2
| | | | | | Anything bigger than 64-bit just map to FPR. llvm-svn: 315946
* [AArch64][LegalizerInfo] Mark s128 G_BITCAST legalQuentin Colombet2017-10-161-1/+3
| | | | | | | We used to mark all G_BITCAST of 128-bit legal but only for vector types. Scalars of this size are just fine as well. llvm-svn: 315945
* Add iterator range MachineRegisterInfo::liveins(), adopt users, NFCKrzysztof Parzyszek2017-10-166-23/+15
| | | | llvm-svn: 315927
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