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* Add support for reading ARM ELF build attributes.Amara Emerson2013-05-032-139/+8
| | | | | | | | | | | Build attribute sections can now be read if they exist via ELFObjectFile, and the llvm-readobj tool has been extended with an option to dump this information if requested. Regression tests are also included which exercise these features. Also update the docs with a fixed ARM ABI link and a new link to the Addenda which provides the build attributes specification. llvm-svn: 181009
* X86: Add target description for btver2; make autodetection logic aware of AVX.Benjamin Kramer2013-05-031-1/+6
| | | | llvm-svn: 181005
* Unbreaking the non-x86 build bots by protecting the AVX test code properly.Aaron Ballman2013-05-031-0/+4
| | | | llvm-svn: 180992
* Correctly testing for AVX support in x86 based off code from Hosts.cpp.Aaron Ballman2013-05-031-1/+18
| | | | llvm-svn: 180991
* Fix missing include in Hexagon code for Release+AssertsReid Kleckner2013-05-031-0/+1
| | | | llvm-svn: 180983
* In MC asm parsing, account for the possibility of whitespace withinJohn McCall2013-05-031-18/+22
| | | | | | | | | | | | | | the "identifier" parsed by the frontend callback by skipping forward until we've consumed a token that ends at the point dictated by the callback. In addition, inform the callback when it's parsing an unevaluated operand (e.g. mov eax, LENGTH A::x) as opposed to an evaluated one (e.g. mov eax, [A::x]). This commit depends on a clang commit. llvm-svn: 180978
* [mips] Handle reading, writing or copying of ccond field of DSP controlAkira Hatanaka2013-05-023-1/+60
| | | | | | | | | | | | register. - Define pseudo instructions which store or load ccond field of the DSP control register. - Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack. - Expand the pseudos before callee-scan save. - Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. llvm-svn: 180969
* reverting r180953Jyotsna Verma2013-05-025-305/+404
| | | | llvm-svn: 180964
* R600: Signed literals are 64bits wideVincent Lejeune2013-05-021-3/+3
| | | | llvm-svn: 180960
* R600: If previous bundle is dot4, PV valid chan is always XVincent Lejeune2013-05-021-38/+51
| | | | llvm-svn: 180959
* R600: Improve asmPrint of ALU clauseVincent Lejeune2013-05-023-4/+20
| | | | llvm-svn: 180957
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-024-13/+45
| | | | llvm-svn: 180956
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-025-404/+305
| | | | llvm-svn: 180953
* Hexagon - Add peephole optimizations for zero extends.Pranav Bhandarkar2013-05-022-0/+40
| | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. llvm-svn: 180946
* [mips] Fix the head Mips16RegisterInfo.cpp commentRichard Sandiford2013-05-021-2/+1
| | | | | | ...aka a test commit. llvm-svn: 180936
* Hexagon: Honor __builtin_expect by using branch probabilities.Jyotsna Verma2013-05-024-37/+122
| | | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp): Given a jump opcode return the right pred.new jump opcode with a taken vs not-taken hint based on branch probabilities provided by the target independent module. * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function. * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode): Enhance existing function use branch probabilities like HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps. llvm-svn: 180923
* R600: Use new tablegen syntax for patternsTom Stellard2013-05-023-447/+381
| | | | | | | | All but two patterns have been converted to the new syntax. The remaining two patterns will require COPY_TO_REGCLASS instructions, which the VLIW DAG Scheduler cannot handle. llvm-svn: 180922
* R600/SI: remove nonsense select patternTom Stellard2013-05-021-8/+1
| | | | | | | | Fortunately this pattern never matched, otherwise we would have generated incorrect code. Signed-off-by: Christian K??nig <christian.koenig@amd.com> llvm-svn: 180921
* 80-col fixup.Michael Liao2013-05-021-2/+3
| | | | llvm-svn: 180915
* Avoid duplicating logic on frame register selecting when lowering eh_returnMichael Liao2013-05-021-9/+11
| | | | | | No functionality change llvm-svn: 180914
* Avoid duplicating logic on frame register selecting when lowering frameaddrMichael Liao2013-05-021-1/+3
| | | | | | No functionality change llvm-svn: 180912
* [mips] Rename class and functions. Simplify code.Akira Hatanaka2013-05-011-26/+29
| | | | | | No functionality changes. llvm-svn: 180897
* This exposes more MCJIT options via the C API:Filip Pizlo2013-05-011-22/+2
| | | | | | | | | | | | | | | | | | | | | CodeModel: It's now possible to create an MCJIT instance with any CodeModel you like. Previously it was only possible to create an MCJIT that used CodeModel::JITDefault. EnableFastISel: It's now possible to turn on the fast instruction selector. The CodeModel option required some trickery. The problem is that previously, we were ensuring future binary compatibility in the MCJITCompilerOptions by mandating that the user bzero's the options struct and passes the sizeof() that he saw; the bindings then bzero the remaining bits. This works great but assumes that the bitwise zero equivalent of any field is a sensible default value. But this is not the case for LLVMCodeModel, or its internal equivalent, llvm::CodeModel::Model. In both of those, the default for a JIT is CodeModel::JITDefault (or LLVMCodeModelJITDefault), which is not bitwise zero. Hence this change introduces LLVMInitializeMCJITCompilerOptions(), which will initialize the user's options struct with defaults. The user will use this in the same way that they would have previously used memset() or bzero(). MCJITCAPITest.cpp illustrates the change, as does the comment in ExecutionEngine.h. llvm-svn: 180893
* Hexagon: Use multiclass for Jump instructions.Jyotsna Verma2013-05-0114-263/+336
| | | | llvm-svn: 180885
* Hexagon: Clear isKill flag on the predicate register inJyotsna Verma2013-05-011-1/+5
| | | | | | PredicateInstruction function. llvm-svn: 180884
* This patch breaks up Wrap.h so that it does not have to include all of Filip Pizlo2013-05-012-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | the things, and renames it to CBindingWrapping.h. I also moved CBindingWrapping.h into Support/. This new file just contains the macros for defining different wrap/unwrap methods. The calls to those macros, as well as any custom wrap/unwrap definitions (like for array of Values for example), are put into corresponding C++ headers. Doing this required some #include surgery, since some .cpp files relied on the fact that including Wrap.h implicitly caused the inclusion of a bunch of other things. This also now means that the C++ headers will include their corresponding C API headers; for example Value.h must include llvm-c/Core.h. I think this is harmless, since the C API headers contain just external function declarations and some C types, so I don't believe there should be any nasty dependency issues here. llvm-svn: 180881
* Put VMOVPQIto64rr in the VRPDI class.Rafael Espindola2013-05-011-3/+3
| | | | | | Patch by Joshua Magee. llvm-svn: 180842
* [mips] Fix handling of instructions which copy to/from accumulator registers.Akira Hatanaka2013-04-307-37/+43
| | | | | | | | | Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. llvm-svn: 180827
* [mips] Instruction selection patterns for DSP-ASE vector select and compareAkira Hatanaka2013-04-305-3/+145
| | | | | | instructions. llvm-svn: 180820
* [mips] Simplify code.Akira Hatanaka2013-04-301-4/+1
| | | | | | No intended functionality changes. llvm-svn: 180807
* [mips] Clear isCommutable bit of instructions which are not commutable.Akira Hatanaka2013-04-301-14/+8
| | | | llvm-svn: 180801
* Text files should not be marked executable.Rafael Espindola2013-04-301-0/+0
| | | | | | Patch by Oliver Pinter. llvm-svn: 180797
* s tightens up the encoding description for ARM post-indexed ldr ↵Mihai Popa2013-04-301-0/+1
| | | | | | instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL. llvm-svn: 180778
* Refactoring patch.Stepan Dyatkovskiy2013-04-305-66/+100
| | | | | | | | | | | | 1. VarArgStyleRegisters: functionality that emits "store" instructions for byval regs moved out into separated method "StoreByValRegs". Before this patch VarArgStyleRegisters had confused use-cases. It was used for both variadic functions and for regular functions with byval parameters. In last case it created new stack-frame and registered it as VarArg frame, that is wrong. This patch replaces VarArgsStyleRegisters usage for byval parameters with StoreByValRegs method. 2. In ARMMachineFunctionInfo, "get/setVarArgsRegSaveSize" was renamed to "get/setArgRegsSaveSize". By the same reason. Sometimes it was used for variadic functions, and sometimes for byval parameters in regular functions. Actually, this property means the size of registers, that keeps arguments, and thats why it was renamed. 3. In ARMISelLowering.cpp, ARMTargetLowering class, in methods computeRegArea and StoreByValRegs, VARegXXXXXX was renamed to ArgRegsXXXXXX still by the same reasons. llvm-svn: 180774
* R600: Always use texture cache for compute shadersVincent Lejeune2013-04-301-2/+6
| | | | | | This will improve the performance of memory reads. llvm-svn: 180762
* R600: use native for aluVincent Lejeune2013-04-304-4/+135
| | | | llvm-svn: 180761
* R600: Packetize instructionsVincent Lejeune2013-04-306-3/+464
| | | | llvm-svn: 180760
* R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chipsVincent Lejeune2013-04-305-32/+105
| | | | llvm-svn: 180759
* R600: Add a Bank Swizzle operandVincent Lejeune2013-04-304-11/+19
| | | | llvm-svn: 180758
* R600: Take inner dependency into tex/vtx clausesVincent Lejeune2013-04-301-0/+34
| | | | llvm-svn: 180757
* R600: Turn TEX/VTX into native instructionsVincent Lejeune2013-04-303-15/+50
| | | | llvm-svn: 180756
* R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune2013-04-309-58/+95
| | | | | | v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache llvm-svn: 180755
* R600: Add some new processor variantsVincent Lejeune2013-04-302-1/+3
| | | | llvm-svn: 180753
* R600: Clean up instruction class definitionsVincent Lejeune2013-04-301-23/+14
| | | | llvm-svn: 180752
* R600: config section now reports use of killgtVincent Lejeune2013-04-301-0/+4
| | | | llvm-svn: 180751
* R600: Use correct CF_END instruction on Northern Island GPUsTom Stellard2013-04-291-1/+1
| | | | llvm-svn: 180735
* R600: Fix encoding of CF_END_{EG, R600} instructionsTom Stellard2013-04-291-0/+1
| | | | | | The EOP bit was not being encoded. llvm-svn: 180734
* AArch64 InstrFormats:Jia Liu2013-04-281-1/+1
| | | | | | delete blank. llvm-svn: 180687
* Make all darwin ppc stubs local.Rafael Espindola2013-04-271-1/+9
| | | | | | | This fixes pr15763. Patch by David Fang. llvm-svn: 180657
* R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTETom Stellard2013-04-261-0/+2
| | | | | | | | | We need to intialize this to something and since clang does not set the shader type attribute and clang is used only for compute shaders, initializing it to COMPUTE seems like the best choice. Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 180620
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