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* [PowerPC] Follow-up to r318436 to get the missed CSE opportunitiesNemanja Ivanovic2017-12-121-1/+65
| | | | | | | | | | | | | | | | | | The last of the three patches that https://reviews.llvm.org/D40348 was broken up into. Canonicalize the materialization of constants so that they are more likely to be CSE'd regardless of the bit-width of the use. If a constant can be materialized using PPC::LI, materialize it the same way always. For example: li 4, -1 li 4, 255 li 4, 65535 are equivalent if the uses only use the low byte. Canonicalize it to the first form. Differential Revision: https://reviews.llvm.org/D40348 llvm-svn: 320473
* Revert r320461 - causing ICE in windows buildssSimon Pilgrim2017-12-124-48/+1032
| | | | | | | | | | [X86] Use regular expressions more aggressively to reduce the number of scheduler entries needed for FMA3 instructions. When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models. This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do. llvm-svn: 320470
* [X86] Use regular expressions more aggressively to reduce the number of ↵Craig Topper2017-12-124-1032/+48
| | | | | | | | | | scheduler entries needed for FMA3 instructions. When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models. This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do. llvm-svn: 320461
* [X86] Use Ld scheduler classes for instructions with folded loads.Craig Topper2017-12-123-41/+41
| | | | llvm-svn: 320459
* [X86] Correct the FMA3 regular expressions in the znver1 scheduler model.Craig Topper2017-12-121-4/+4
| | | | llvm-svn: 320458
* Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversionRichard Trieu2017-12-113-92/+29
| | | | | | | | See bug https://bugs.llvm.org/show_bug.cgi?id=35631 r318704 is giving a fatal error on some code with unsigned to floating point conversions. llvm-svn: 320429
* LSR: Check more intrinsic pointer operandsMatt Arsenault2017-12-112-0/+28
| | | | llvm-svn: 320424
* [PowerPC] Partially enable the ISEL expansion pass.Tony Jiang2017-12-111-21/+64
| | | | | | | | | | | The pass to expand ISEL instructions into if-then-else sequences in patch D23630 is currently disabled. This patch partially enable it by always removing the unnecessary ISELs (all registers used by the ISELs are the same one) and folding the ISELs which have the same input registers into unconditional copies. Differential Revision: https://reviews.llvm.org/D40497 llvm-svn: 320414
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-1152-5590/+11596
| | | | llvm-svn: 320404
* Normalize line endings. NFCI.Simon Pilgrim2017-12-111-30/+30
| | | | llvm-svn: 320389
* [X86] Add LWP schedule testsSimon Pilgrim2017-12-111-2/+2
| | | | | | Tag LWP instructions as WriteSystem llvm-svn: 320387
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-118-69/+164
| | | | | | | | | | | | See bugs 35494 and 35559: https://bugs.llvm.org/show_bug.cgi?id=35494 https://bugs.llvm.org/show_bug.cgi?id=35559 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41007 llvm-svn: 320375
* [Hexagon] Crash in instruction selection for insert_vector_elt for HVXKrzysztof Parzyszek2017-12-111-1/+1
| | | | | | | | A wrong type was passed to insertVector, causing an out-of-bounds value to be added an an operand to HexagonISD::INSERT. This later failed in instruction selection. llvm-svn: 320369
* [PowerPC] Sign-extend negative constant storesNemanja Ivanovic2017-12-111-2/+6
| | | | | | | | | | | | | Second part of https://reviews.llvm.org/D40348. Revision r318436 has extended all constants feeding a store to 64 bits to allow for CSE on the SDAG. However, negative constants were zero extended which made the constant being loaded appear to be a positive value larger than 16 bits. This resulted in long sequences to materialize such constants rather than simply a "load immediate". This patch just sign-extends those updated constants so that they remain 16-bit signed immediates if they started out that way. llvm-svn: 320368
* [RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury2017-12-114-48/+373
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
* [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestoreAlex Bradbury2017-12-111-0/+5
| | | | llvm-svn: 320358
* [RISCV] Implement prolog and epilog insertionAlex Bradbury2017-12-112-3/+159
| | | | | | | | | | As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 llvm-svn: 320357
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-12-112-20/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 - fixes PR34564 - fixes PR35103 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 320355
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-117-29/+85
| | | | | | | | | | | | | | | | Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-1120-1072/+113
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* [AVR] Implement some missing code pathsDylan McKay2017-12-112-4/+19
| | | | | | This has been broken since r320009. llvm-svn: 320348
* [AVR] Fix incorrectly-calculated AVRMCExpr evaluationsDylan McKay2017-12-111-12/+9
| | | | | | This has been broken since r320009. llvm-svn: 320347
* [X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the ↵Craig Topper2017-12-101-4/+4
| | | | | | skylake server sheduler model llvm-svn: 320326
* [X86] Rename some instructions that start with Int_ to have the _Int at the end.Craig Topper2017-12-109-199/+199
| | | | | | | | This matches AVX512 version and is more consistent overall. And improves our scheduler models. In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses. llvm-svn: 320325
* [X86][X87] Fix typo in znver1 FIST/FISTT schedule patternsSimon Pilgrim2017-12-101-1/+1
| | | | llvm-svn: 320322
* [X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper ↵Craig Topper2017-12-102-17/+17
| | | | | | | | suffix. Fix the scheduling information for some of them. Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)' llvm-svn: 320320
* [X86] Add VCVTQQ2PS to the skylake server scheduler models.Craig Topper2017-12-101-0/+6
| | | | llvm-svn: 320319
* [X86] Add VPMULLWZ256 to the skylake server scheduler modelCraig Topper2017-12-101-0/+2
| | | | llvm-svn: 320318
* [X86] Add 256/512-bit EVEX VPSADBW instructions to skylake server scheduler ↵Craig Topper2017-12-101-2/+4
| | | | | | model. llvm-svn: 320317
* [X86] Fix a few instructions that were named Z512 instead of just Z.Craig Topper2017-12-104-15/+15
| | | | | | This makes things consistent with our normal instruction naming. llvm-svn: 320316
* [X86] Add VPSRLWZrr to skylake server scheduler model.Craig Topper2017-12-101-0/+1
| | | | llvm-svn: 320315
* [X86] Add VPUNPCKLWDZrr to skylake server scheduler model.Craig Topper2017-12-101-0/+1
| | | | llvm-svn: 320314
* [X86] Adjust tablegen includes so we can use Instructions in scheduler ↵Craig Topper2017-12-102-26/+25
| | | | | | | | models instead of just instregexs. This separates the CPU specific scheduler model includes to occur after the instructions. Moves the instruction includes between the basic scheduler information and the CPU specific scheduler models. llvm-svn: 320313
* [X86] Flag BroadWell scheduler model as completeSimon Pilgrim2017-12-101-4/+3
| | | | | | Locally tag COPY as WriteMove, which has caused some reg-reg + reg-mem instruction tests to reorder. llvm-svn: 320308
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-12-101-3/+3
| | | | llvm-svn: 320306
* [X86] Flag ZNVER1 scheduler model as completeSimon Pilgrim2017-12-101-6/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320304
* [X86] Flag SLM scheduler model as completeSimon Pilgrim2017-12-101-5/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320303
* [X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classesSimon Pilgrim2017-12-102-3/+9
| | | | llvm-svn: 320302
* [X86] Tag SSE4A instructions as SSE INTALU scheduler classesSimon Pilgrim2017-12-101-4/+8
| | | | llvm-svn: 320301
* [X86] Flag BTVER2 scheduler model as completeSimon Pilgrim2017-12-101-4/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320300
* [X86] Tag ADJSTACK instructions as INTALU scheduler classSimon Pilgrim2017-12-101-11/+9
| | | | llvm-svn: 320299
* [X86] Tag MORESTACK instructions as ret scheduler classSimon Pilgrim2017-12-101-3/+3
| | | | llvm-svn: 320296
* [X86] Fix duplicate entries in skylake server scheduler model by changing ↵Craig Topper2017-12-101-8/+8
| | | | | | | | Z128 to Z256 Based on the fact that the 'Y' version of the instruction is next to this, I assume Z256 is the intended value. llvm-svn: 320295
* [X86] Add MOVQI2PQIrm, MOVSDmr, and MOVSDrm to scheduler informationCraig Topper2017-12-105-0/+15
| | | | | | The VEX versions were present but not the legacy SSE versions. llvm-svn: 320294
* [X86] Add LEA64_32r to scheduler models for ↵Craig Topper2017-12-105-5/+5
| | | | | | Sandybridge,Haswell,Broadwell,Skylake llvm-svn: 320293
* [X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,SkylakeCraig Topper2017-12-104-16/+16
| | | | | | Sandy Bridge is also missing it, but it has other issues. See PR35590. llvm-svn: 320292
* [X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. ↵Craig Topper2017-12-105-80/+80
| | | | | | Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP. llvm-svn: 320291
* [X86] Rename some instructions so that 'b' is added as a suffix instead of ↵Craig Topper2017-12-103-22/+22
| | | | | | replacing an 'r' llvm-svn: 320290
* [X86] Add CMPSDrr/rm to the scheduler models.Craig Topper2017-12-105-0/+10
| | | | | | Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing. llvm-svn: 320289
* PowerPC: support external pid instructions in MC layer.Tim Northover2017-12-101-0/+57
| | | | | | | | | | | This adds assembly & disassembly support for the e500mc "external pid" instructions. See https://reviews.llvm.org/D39249. Patch by vit9696 <vit9696@avp.su> llvm-svn: 320287
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