diff options
| author | Craig Topper <craig.topper@intel.com> | 2017-12-10 09:14:42 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-10 09:14:42 +0000 |
| commit | 28e55386acf5f6875278f6badc6f3915e1b9e05b (patch) | |
| tree | 2caa1bc899722ec7061c74cb01fb78c1effb37ab /llvm/lib/Target | |
| parent | 8ade4640f3edf8fe687dfef567f6dc0529e7803e (diff) | |
| download | bcm5719-llvm-28e55386acf5f6875278f6badc6f3915e1b9e05b.tar.gz bcm5719-llvm-28e55386acf5f6875278f6badc6f3915e1b9e05b.zip | |
[X86] Add LEA64_32r to scheduler models for Sandybridge,Haswell,Broadwell,Skylake
llvm-svn: 320293
Diffstat (limited to 'llvm/lib/Target')
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedBroadwell.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 2 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 50d9452874d..0f0b4a47778 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -708,7 +708,7 @@ def: InstRW<[BWWriteResGroup7], (instregex "BLSR32rr")>; def: InstRW<[BWWriteResGroup7], (instregex "BLSR64rr")>; def: InstRW<[BWWriteResGroup7], (instregex "BZHI32rr")>; def: InstRW<[BWWriteResGroup7], (instregex "BZHI64rr")>; -def: InstRW<[BWWriteResGroup7], (instregex "LEA(16|32|64)r")>; +def: InstRW<[BWWriteResGroup7], (instregex "LEA(16|32|64)(_32)?r")>; def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSBrr64")>; def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSDrr64")>; def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSWrr64")>; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index d32d3796a46..4cc55443394 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -1252,7 +1252,7 @@ def: InstRW<[HWWriteResGroup8], (instregex "BLSR32rr")>; def: InstRW<[HWWriteResGroup8], (instregex "BLSR64rr")>; def: InstRW<[HWWriteResGroup8], (instregex "BZHI32rr")>; def: InstRW<[HWWriteResGroup8], (instregex "BZHI64rr")>; -def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)r")>; +def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>; def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr64")>; def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr64")>; def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSWrr64")>; diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index dfebd3ae124..5e1cfbd7b67 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -469,7 +469,7 @@ def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)r")>; +def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)(_32)?r")>; def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { let Latency = 1; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index cde59e89927..1c00296f0ae 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -821,7 +821,7 @@ def: InstRW<[SKLWriteResGroup8], (instregex "BLSR32rr")>; def: InstRW<[SKLWriteResGroup8], (instregex "BLSR64rr")>; def: InstRW<[SKLWriteResGroup8], (instregex "BZHI32rr")>; def: InstRW<[SKLWriteResGroup8], (instregex "BZHI64rr")>; -def: InstRW<[SKLWriteResGroup8], (instregex "LEA(16|32|64)r")>; +def: InstRW<[SKLWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>; def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { let Latency = 1; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index fe3dfd5879c..94ec2d885f1 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -1124,7 +1124,7 @@ def: InstRW<[SKXWriteResGroup8], (instregex "BLSR32rr")>; def: InstRW<[SKXWriteResGroup8], (instregex "BLSR64rr")>; def: InstRW<[SKXWriteResGroup8], (instregex "BZHI32rr")>; def: InstRW<[SKXWriteResGroup8], (instregex "BZHI64rr")>; -def: InstRW<[SKXWriteResGroup8], (instregex "LEA(16|32|64)r")>; +def: InstRW<[SKXWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>; def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> { let Latency = 1; |
