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* Change encodeU/SLEB128 to pad to certain number of bytesSam Clegg2017-09-151-5/+2
* [llvm] Fix some typos. NFC.Mandeep Singh Grang2017-09-151-1/+1
* Revert r313343 "[X86] PR32755 : Improvement in CodeGen instruction selection ...Hans Wennborg2017-09-152-479/+10
* [X86] Prefer VPERMQ over VPERM2F128 for any unary shuffle, not just the ones ...Craig Topper2017-09-151-3/+4
* [X86] Use SDNode::ops() instead of makeArrayRef and op_begin(). NFCICraig Topper2017-09-151-5/+5
* [X86] Don't create i64 constants on 32-bit targets when lowering v64i1 consta...Craig Topper2017-09-151-0/+12
* [X86] Add isel pattern infrastructure to begin recognizing when we're inserti...Craig Topper2017-09-151-0/+59
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-1529-13785/+2407
* [AArch64] allow v8f16 types when FullFP16 is supportedSjoerd Meijer2017-09-151-33/+31
* [X86] PR32755 : Improvement in CodeGen instruction selection for LEAs.Jatin Bhateja2017-09-152-10/+479
* [X86] Remove an unnecessary SmallVector from LowerBUILD_VECTOR.Craig Topper2017-09-141-4/+2
* Fix warnings in r313297.Jan Sjodin2017-09-142-5/+3
* AMDGPU: Fix violating constant bus restrictionMatt Arsenault2017-09-141-4/+5
* Add AddresSpace to PseudoSourceValue.Jan Sjodin2017-09-144-4/+29
* AMDGPU: Fix assert on alloca of array of structMatt Arsenault2017-09-141-6/+5
* AMDGPU: Stop modifying SP in call sequencesMatt Arsenault2017-09-141-3/+3
* [mips] Implement the 'dext' aliases and it's disassembly alias.Simon Dardis2017-09-145-43/+162
* AMDGPU: Make frame register caller preservedMatt Arsenault2017-09-142-10/+16
* [mips] Implement the 'dins' aliases.Simon Dardis2017-09-145-25/+139
* Test commit.Aleksandar Beserminji2017-09-141-1/+1
* [Hexagon] Make getMemAccessSize return size in bytesKrzysztof Parzyszek2017-09-147-58/+65
* [X86] When applying the shuffle-to-zero-extend transformation on floating poi...Ayman Musa2017-09-141-4/+9
* [mips] Pick the right variant of DINS upfront and enable target instruction v...Simon Dardis2017-09-148-44/+119
* AMDGPU: Don't spill SP reg like a normal CSRMatt Arsenault2017-09-133-0/+16
* Allow target to decide when to cluster loads/stores in mischedStanislav Mekhanoshin2017-09-134-2/+47
* AMDGPU: Handle coldcc in more placesMatt Arsenault2017-09-131-0/+2
* Refactoring the stride 4 code in the X86interleavedaccess NFCMichael Zuckerman2017-09-131-34/+32
* [mips] correct operand range for DINSM instructionPetar Jovanovic2017-09-131-1/+1
* [Power9] Add missing instructions: extswsli, popcntbStefan Pintilie2017-09-132-0/+22
* [GlobalISel][X86] support G_FPEXT operation.Igor Breger2017-09-132-3/+15
* [X86] [PATCH] [intrinsics] Lowering X86 ABS intrinsics to IR. (llvm)Uriel Korach2017-09-131-18/+0
* [X86] Adding X86 Processor FamiliesMohammed Agabaria2017-09-133-5/+59
* [X86] Make sure we emit a SUBREG_TO_REG after the MOV32ri when creating a BEX...Craig Topper2017-09-131-2/+9
* [X86 CodeGen] Optimization of ZeroExtendLoad for v2i8 vectorElena Demikhovsky2017-09-131-0/+1
* [X86] Use isUInt<32> to simplify some code. NFCCraig Topper2017-09-131-1/+1
* [Fuchsia] Magenta -> ZirconPetr Hosek2017-09-132-4/+4
* [WebAssembly] Add sign extend instructions from atomics proposalDerek Schuff2017-09-132-2/+24
* [x86] eliminate unnecessary vector compare for AVX masked storeSanjay Patel2017-09-121-2/+27
* [mips] handle UImm16_AltRelaxed match typePetar Jovanovic2017-09-121-0/+1
* [AArch64][GlobalISel] Select all fpexts.Ahmed Bougacha2017-09-122-33/+7
* [AArch64][GlobalISel] Select all fptruncs.Ahmed Bougacha2017-09-121-28/+3
* Update branch coalescing to be a PowerPC specific passLei Huang2017-09-124-0/+794
* bpf: Add BPF AsmParser support in LLVMYonghong Song2017-09-125-1/+500
* [X86] Move matching of (and (srl/sra, C), (1<<C) - 1) to BEXTR/BEXTRI instruc...Craig Topper2017-09-124-52/+92
* Revert r313009 "[ARM] Use ADDCARRY / SUBCARRY"Hans Wennborg2017-09-122-168/+20
* [SystemZ] Add the CoveredBySubRegs bit to GPR64, GPR128 and FPR128 registers.Jonas Paulsson2017-09-121-0/+3
* [AArch64] ISel: Add some debug messages to LowerBUILDVECTOR. NFC.Sjoerd Meijer2017-09-121-19/+59
* [X86] Lower _mm[256|512]_[mask[z]]_avg_epu[8|16] intrinsics to native llvm IRYael Tsafrir2017-09-121-10/+0
* [ARM] Fix typo when creating ISD::SUB nodesRoger Ferrer Ibanez2017-09-121-5/+5
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-09-122-20/+168
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