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* This reverts r155000.Joey Gouly2013-06-201-6/+1
| | | | | | | | | The cdp2 instruction should have the same restrictions as cdp on the co-processor registers. VFP instructions on v8/AArch32 share the same encoding space as cdp2. llvm-svn: 184445
* [PowerPC] Remove unused parameterUlrich Weigand2013-06-203-14/+14
| | | | | | | The isDarwin parameter to the llvm::LowerPPCMachineInstrToMCInst routine is now no longer needed; remove it. llvm-svn: 184441
* [PowerPC] Add missing build dependencyUlrich Weigand2013-06-201-1/+1
| | | | | | | This (hopefully) fixes build failures resulting from r184436; the PowerPC asm parser now depends on PowerPC target expresssions. llvm-svn: 184439
* [PowerPC] Optimize @ha/@l constructsUlrich Weigand2013-06-204-46/+144
| | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for having the assembler optimize fixups to constructs like "symbol@ha" or "symbol@l" if "symbol" can be resolved at assembler time. This optimization is already present in the PPCMCExpr.cpp code for handling PPC_HA16/PPC_LO16 target expressions. However, those target expression were used only on Darwin targets. This patch changes target expression code so that they are usable also with the GNU assembler (using the @ha / @l syntax instead of the ha16() / lo16() syntax), and changes the MCInst lowering code to generate those target expressions where appropriate. It also changes the asm parser to generate HA16/LO16 target expressions when parsing assembler source that uses the @ha / @l modifiers. The effect is that now the above- mentioned optimization automatically becomes available for those situations too. llvm-svn: 184436
* [PowerPC] Support compare mnemonics with implied CR0Ulrich Weigand2013-06-201-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + llvm-svn: 184435
* Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU ↵Vladimir Medic2013-06-201-48/+58
| | | | | | registers. llvm-svn: 184411
* Don't pass in the TargetInstrInfo into the register info object. It doesn't ↵Bill Wendling2013-06-193-4/+3
| | | | | | use it. llvm-svn: 184369
* DebugInfo: PR14763/r183329 correct the location of indirect parametersDavid Blaikie2013-06-192-4/+6
| | | | | | | | | | | | | | | | We had been papering over a problem with location info for non-trivial types passed by value by emitting their type as references (this caused the debugger to interpret the location information correctly, but broke the type of the function). r183329 corrected the type information but lead to the debugger interpreting the pointer parameter as the value - the debug info describing the location needed an extra dereference. Use a new flag in DIVariable to add the extra indirection (either by promoting an existing DW_OP_reg (parameter passed in a register) to DW_OP_breg + 0 or by adding DW_OP_deref to an existing DW_OP_breg + n (parameter passed on the stack). llvm-svn: 184368
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-1915-59/+78
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-1/+1
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184352
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-193-3/+3
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184349
* Move StructurizeCFG out of R600 to generic Transforms.Matt Arsenault2013-06-193-898/+1
| | | | | | Register it with PassManager llvm-svn: 184343
* The RenderMethod field in RegisterOperand class sets the name of the method ↵Vladimir Medic2013-06-192-19/+10
| | | | | | on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp llvm-svn: 184292
* Use GetUnderlyingObject instead of custom functionMatt Arsenault2013-06-181-58/+20
| | | | llvm-svn: 184261
* ARM: Add optional datatype suffix to NEON mvn asm syntax.Jim Grosbach2013-06-181-1/+6
| | | | | | rdar://14194152 llvm-svn: 184244
* [ARMTargetLowering] ARMISD::{SUB,ADD}{C,E} second result is a boolean ↵Michael Gottesman2013-06-181-1/+11
| | | | | | implying that upper bits are always 0. llvm-svn: 184231
* Converted an overly aggressive assert to a conditional check in ↵Michael Gottesman2013-06-181-2/+5
| | | | | | | | | | | | | | | | | | AddCombineTo64bitMLAL. Said assert assumes that ADDC will always have a glue node as its second argument and is checked before we even know that we are actually performing the relevant MLAL optimization. This is incorrect since on ARM we *CAN* codegen ADDC with a use list based second argument. Thus to have both effects, I converted the assert to a conditional check which if it fails we do not perform the optimization. In terms of tests I can not produce an ADDC from the IR level until I get in my multiprecision optimization patch which is forthcoming. The tests for said patch would cause this assert to fail implying that said tests will provide the relevant tests. llvm-svn: 184230
* Fix 80 col violation.Nadav Rotem2013-06-181-3/+6
| | | | llvm-svn: 184228
* Change the arm assembler to support this from the v7c spec:Kevin Enderby2013-06-181-1/+11
| | | | | | | | | | | | | | | "When assembling to the ARM instruction set, the .N qualifier produces an assembler error and the .W qualifier has no effect." In the pre-matcher handler in the asm parser the ".w" (wide) qualifier when in ARM mode is now discarded. And an error message is now produced when the ".n" (narrow) qualifier is used in ARM mode. Test cases for these were added. rdar://14064574 llvm-svn: 184224
* Mips ELF: Mark object file as ABI compliant Jack Carter2013-06-182-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When producing objects that are abi compliant we are marking neither the object file nor the assembly file correctly and thus generate warnings. We need to set the EF_CPIC flag in the ELF header when generating direct object. Note that the warning is only generated when compiling without PIC. When compiling with clang the warning will be suppressed by supplying: -Wa,-mno-shared -Wa,-call_nonpic Also the following directive should also be added: .option pic0 when compiling without PIC, This eliminates the need for supplying: -mno-shared -call_nonpic on the assembler command line. Patch by Douglas Gilmore llvm-svn: 184220
* Reduce indentation.David Blaikie2013-06-181-53/+55
| | | | llvm-svn: 184213
* Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.Stefanus Du Toit2013-06-181-0/+7
| | | | | | | | For decoding, keep the current behavior of always decoding these as their REP versions. In the future, this could be improved to recognize the cases where these behave as XACQUIRE and XRELEASE and decode them as such. llvm-svn: 184207
* ARM: fix literal load with positive offset encodingAmaury de la Vieuville2013-06-183-5/+7
| | | | | | | | | | | | When using a positive offset, literal loads where encoded as if it was negative, because: - The sign bit was not assigned to an operand - The addrmode_imm12 operand was not encoding the sign bit correctly This patch also makes the assembler look at the .w/.n specifier for loads. llvm-svn: 184182
* ARM: add operands pre-writeback variants when neededAmaury de la Vieuville2013-06-183-40/+61
| | | | llvm-svn: 184181
* ARM: fix thumb literal loads decodingAmaury de la Vieuville2013-06-183-29/+238
| | | | | | | | This fixes two previous issues: - Negative offsets were not correctly disassembled - The decoded opcodes were not the right one llvm-svn: 184180
* ARM: thumb stores cannot use PC as dest registerAmaury de la Vieuville2013-06-181-0/+37
| | | | llvm-svn: 184179
* Use pointers to the MCAsmInfo and MCRegInfo.Bill Wendling2013-06-1816-88/+88
| | | | | | | | | Someone may want to do something crazy, like replace these objects if they change or something. No functionality change intended. llvm-svn: 184175
* Remove dead prototype.Bill Wendling2013-06-181-2/+0
| | | | llvm-svn: 184173
* R600: PV stores Reg id, not indexVincent Lejeune2013-06-171-1/+1
| | | | llvm-svn: 184117
* R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.Vincent Lejeune2013-06-171-14/+16
| | | | | | | Fixes rv7x0 bug in Heaven reported here: https://bugs.freedesktop.org/show_bug.cgi?id=64257 llvm-svn: 184116
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-1629-369/+9
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. llvm-svn: 184067
* Debug Info: Simplify Frame Index handling in DBG_VALUE Machine InstructionsDavid Blaikie2013-06-161-6/+1
| | | | | | | | | | | | | | | | | | | | Rather than using the full power of target-specific addressing modes in DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This reduces the complexity of debug info handling down to two representations of values (reg+offset and frame index+offset) rather than three or four. Ideally we could ensure that frame indicies had been eliminated by the time we reached an assembly or dwarf generation, but I haven't spent the time to figure out where the FIs are leaking through into that & whether there's a good place to convert them. Some FI+offset=>reg+offset conversion is done (see PrologEpilogInserter, for example) which is necessary for some SelectionDAG assumptions about registers, I believe, but it might be possible to make this a more thorough conversion & ensure there are no remaining FIs no matter how instruction selection is performed. llvm-svn: 184066
* Support BufferSize on ProcResGroup for unified MOp schedulers.Andrew Trick2013-06-152-0/+11
| | | | | | And add Sandybridge/Haswell resource buffers. llvm-svn: 184034
* Update machine models. Specify buffer sizes for OOO processors.Andrew Trick2013-06-156-10/+10
| | | | llvm-svn: 184033
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-157-16/+4
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. llvm-svn: 184032
* R600: Add SI load support for v[24]i32 and store for v2i32Tom Stellard2013-06-151-0/+5
| | | | | | | | | | | Also add a seperate vector lit test file, since r600 doesn't seem to handle v2i32 load/store yet, but we can test both for SI. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> llvm-svn: 184021
* R600: Use correct encoding for Vertex Fetch instructions on CaymanTom Stellard2013-06-143-156/+294
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184016
* R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on CaymanTom Stellard2013-06-142-37/+57
| | | | | | | | | We were using RAT_INST_STORE_RAW, which seemed to work, but the docs say this instruction doesn't exist for Cayman, so it's probably safer to use a documented instruction instead. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184015
* R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg classTom Stellard2013-06-142-50/+68
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184014
* R600: Move instruction encoding definitions into a separate .td fileTom Stellard2013-06-142-362/+393
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184013
* ARM: fix thumb coprocessor instruction with pre-writeback disassemblyAmaury de la Vieuville2013-06-141-1/+1
| | | | | | | was stc2 p0, c0, [r0]! instead of stc2 p0, c0, [r0,#0]! llvm-svn: 183975
* X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX ↵Benjamin Kramer2013-06-141-7/+8
| | | | | | | | equivalent. Give it the right register format so we can also emit it when AVX is enabled. llvm-svn: 183971
* Enable FastISel on ARM for Linux and NaCl, not MCJITJF Bastien2013-06-141-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a resubmit of r182877, which was reverted because it broken MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only enabled for iOS. I've CC'ed people from the original review and revert. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl, but not MCJIT. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. All the tests also pass on x86 make check-all. I also re-ran the check-all tests that failed on ARM, and they all seem to pass. llvm-svn: 183966
* R600: Don't try to fix reg class when copying IMPLICIT_DEF to a registerTom Stellard2013-06-131-1/+2
| | | | | | | | | The test case for this is way too complex to be useful as a lit test, and I was unable to reduce it. https://bugs.freedesktop.org/show_bug.cgi?id=65438 llvm-svn: 183937
* Mips: Remove global set.Benjamin Kramer2013-06-132-57/+68
| | | | | | Backends shouldn't retain any global state. No functionality change. llvm-svn: 183927
* ARM: fix B decodingAmaury de la Vieuville2013-06-131-1/+1
| | | | llvm-svn: 183914
* ARM: fix t2am_imm8_offset operand printing for imm=#-0Amaury de la Vieuville2013-06-131-1/+3
| | | | llvm-svn: 183913
* X86: Make the cmov aliases work with intel syntax too.Benjamin Kramer2013-06-131-21/+25
| | | | llvm-svn: 183907
* Revert r183854 (PPC: Fix switch warnings from r183841)David Blaikie2013-06-122-3/+2
| | | | | | | Now that the PRED_BAD has been removed, this is failing the Clang -Werror build due to -Wcovered-switch-default. llvm-svn: 183863
* [PowerPC] Remove PRED_BAD from PPC::Predicate enumeration.Bill Schmidt2013-06-121-2/+1
| | | | | | | | I'm taking David Blaikie's suggestion to use an Optional<PPC::Predicate> return value instead. That's the right solution for this problem. Thanks for pointing out that possibility! llvm-svn: 183858
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