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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-06-14 22:12:19 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-06-14 22:12:19 +0000 |
| commit | d99b7932aeb66038e754131b6ad3e0040d991305 (patch) | |
| tree | 4b3160b8889d6c1e4cf0ad7edba470fcebd498ad /llvm/lib/Target | |
| parent | 3d0823f1cde5b3f68c4207e3d7f8a030629cae66 (diff) | |
| download | bcm5719-llvm-d99b7932aeb66038e754131b6ad3e0040d991305.tar.gz bcm5719-llvm-d99b7932aeb66038e754131b6ad3e0040d991305.zip | |
R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184014
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/R600/R600InstrFormats.td | 45 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/R600Instructions.td | 73 |
2 files changed, 68 insertions, 50 deletions
diff --git a/llvm/lib/Target/R600/R600InstrFormats.td b/llvm/lib/Target/R600/R600InstrFormats.td index 7cc48f454c9..618004fd269 100644 --- a/llvm/lib/Target/R600/R600InstrFormats.td +++ b/llvm/lib/Target/R600/R600InstrFormats.td @@ -390,3 +390,48 @@ class CF_ALU_WORD1 { let Word1{30} = WHOLE_QUAD_MODE; let Word1{31} = BARRIER; } + +class CF_ALLOC_EXPORT_WORD0_RAT { + field bits<32> Word0; + + bits<4> rat_id; + bits<6> rat_inst; + bits<2> rim; + bits<2> type; + bits<7> rw_gpr; + bits<1> rw_rel; + bits<7> index_gpr; + bits<2> elem_size; + + let Word0{3-0} = rat_id; + let Word0{9-4} = rat_inst; + let Word0{10} = 0; // Reserved + let Word0{12-11} = rim; + let Word0{14-13} = type; + let Word0{21-15} = rw_gpr; + let Word0{22} = rw_rel; + let Word0{29-23} = index_gpr; + let Word0{31-30} = elem_size; +} + +class CF_ALLOC_EXPORT_WORD1_BUF { + field bits<32> Word1; + + bits<12> array_size; + bits<4> comp_mask; + bits<4> burst_count; + bits<1> vpm; + bits<1> eop; + bits<8> cf_inst; + bits<1> mark; + bits<1> barrier; + + let Word1{11-0} = array_size; + let Word1{15-12} = comp_mask; + let Word1{19-16} = burst_count; + let Word1{20} = vpm; + let Word1{21} = eop; + let Word1{29-22} = cf_inst; + let Word1{30} = mark; + let Word1{31} = barrier; +} diff --git a/llvm/lib/Target/R600/R600Instructions.td b/llvm/lib/Target/R600/R600Instructions.td index 7512cf44676..9716fcf9dd1 100644 --- a/llvm/lib/Target/R600/R600Instructions.td +++ b/llvm/lib/Target/R600/R600Instructions.td @@ -235,45 +235,18 @@ def TEX_SHADOW_ARRAY : PatLeaf< }] >; -class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs, +class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, dag outs, dag ins, string asm, list<dag> pattern> : - InstR600ISA <outs, ins, asm, pattern> { - bits<7> RW_GPR; - bits<7> INDEX_GPR; - - bits<2> RIM; - bits<2> TYPE; - bits<1> RW_REL; - bits<2> ELEM_SIZE; - - bits<12> ARRAY_SIZE; - bits<4> COMP_MASK; - bits<4> BURST_COUNT; - bits<1> VPM; - bits<1> eop; - bits<1> MARK; - bits<1> BARRIER; - - // CF_ALLOC_EXPORT_WORD0_RAT - let Inst{3-0} = rat_id; - let Inst{9-4} = rat_inst; - let Inst{10} = 0; // Reserved - let Inst{12-11} = RIM; - let Inst{14-13} = TYPE; - let Inst{21-15} = RW_GPR; - let Inst{22} = RW_REL; - let Inst{29-23} = INDEX_GPR; - let Inst{31-30} = ELEM_SIZE; - - // CF_ALLOC_EXPORT_WORD1_BUF - let Inst{43-32} = ARRAY_SIZE; - let Inst{47-44} = COMP_MASK; - let Inst{51-48} = BURST_COUNT; - let Inst{52} = VPM; - let Inst{53} = eop; - let Inst{61-54} = cf_inst; - let Inst{62} = MARK; - let Inst{63} = BARRIER; + InstR600ISA <outs, ins, asm, pattern>, + CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF { + + let cf_inst = cfinst; + let rat_inst = ratinst; + let rat_id = ratid; + + let Inst{31-0} = Word0; + let Inst{63-32} = Word1; + } class LoadParamFrag <PatFrag load_type> : PatFrag < @@ -1396,21 +1369,21 @@ let hasSideEffects = 1 in { //===----------------------------------------------------------------------===// let usesCustomInserter = 1 in { -class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name, +class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> mask, string name, list<dag> pattern> : EG_CF_RAT <0x57, 0x2, 0, (outs), ins, name, pattern> { - let RIM = 0; + let rim = 0; // XXX: Have a separate instruction for non-indexed writes. - let TYPE = 1; - let RW_REL = 0; - let ELEM_SIZE = 0; - - let ARRAY_SIZE = 0; - let COMP_MASK = comp_mask; - let BURST_COUNT = 0; - let VPM = 0; - let MARK = 0; - let BARRIER = 1; + let type = 1; + let rw_rel = 0; + let elem_size = 0; + + let array_size = 0; + let comp_mask = mask; + let burst_count = 0; + let vpm = 0; + let mark = 0; + let barrier = 1; } } // End usesCustomInserter = 1 |

