summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware ↵Artem Tamazov2016-04-272-13/+42
| | | | | | | | | | | | registers. Possibility to specify code of hardware register kept. Disassemble to symbolic name, if name is known. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19335 llvm-svn: 267724
* Revert r267649, it caused PR27539.Nico Weber2016-04-271-136/+0
| | | | llvm-svn: 267723
* [mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU ↵Zlatko Buljan2016-04-275-20/+70
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
* [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, ↵Zlatko Buljan2016-04-273-12/+41
| | | | | | | | SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
* [ppc64] fix bug in prologue that mfocrf's cr operand should be explict state ↵Chuang-Yu Cheng2016-04-271-4/+10
| | | | | | | | | | | | instead of implicit This fixes PR27414 Reviewers: kbarton mgrang tjablin http://reviews.llvm.org/D19255 llvm-svn: 267660
* [X86] Set AddPristinesAndCSRs to FixupBW LivePhysRegs. NFC.Ahmed Bougacha2016-04-271-1/+2
| | | | | | | | | | | | | We run after PEI, so we need to AddPristinesAndCSRs. In practice, that makes no difference here, because we only ask about liveness of super-registers of defined GR8/GR16 registers, so they can't be pristine. Still, it's the correct thing to do. Thanks to Quentin for noticing! Follow-up to r267495. llvm-svn: 267658
* [X86] Don't assume that MMX extractelts are from index 0.Ahmed Bougacha2016-04-271-1/+3
| | | | | | | It's probably the case for all 3 MMX users out there, but with hand-crafted IR, you can trigger selection failures. Fix that. llvm-svn: 267652
* [X86] Re-enable MMX i32 extractelt combine.Ahmed Bougacha2016-04-271-10/+3
| | | | | | | | | This effectively adds back the extractelt combine removed by r262358: the direct case can still occur (because x86_mmx is special, see r262446), but it's the indirect case that's now superseded by the generic combine. llvm-svn: 267651
* Detects the SAD pattern on X86 so that much better code will be emitted once ↵Cong Hou2016-04-271-0/+136
| | | | | | | | the pattern is matched. Differential revision: http://reviews.llvm.org/D14840 llvm-svn: 267649
* Add optimization bisect opt-in calls for SystemZ passesAndrew Kaylor2016-04-263-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D19562 llvm-svn: 267636
* Add optimization bisect opt-in calls for NVPTX passesAndrew Kaylor2016-04-265-1/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D19518 llvm-svn: 267635
* [X86] Make sure it is safe to clobber EFLAGS, if need be, when choosingQuentin Colombet2016-04-262-0/+16
| | | | | | | | | | | | | | | the prologue. Do not use basic blocks that have EFLAGS live-in as prologue if we need to realign the stack. Realigning the stack uses AND instruction and this clobbers EFLAGS. An other alternative would have been to save and restore EFLAGS around the stack realignment code, but this is likely inefficient. Fixes PR27531. llvm-svn: 267634
* [X86] Teach the expansion of copy instructions how to do proper liveness.Quentin Colombet2016-04-261-15/+22
| | | | | | | When the simple analysis provided by MachineBasicBlock::computeRegisterLiveness fails, fall back on the LivePhysReg utility. llvm-svn: 267623
* [NVPTX] Fix some usages of CodeGenOpt::None.Jingyue Wu2016-04-261-5/+9
| | | | | | | | | | NVPTXLowerKernelArgs is required for correctness, so it should not be guarded by CodeGenOpt::None. NVPTXPeephole is optimization only, so it should be skipped when CodeGenOpt::None. llvm-svn: 267619
* Optimization bisect support in X86-specific passesAndrew Kaylor2016-04-265-3/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D19439 llvm-svn: 267608
* [CodeGen] Add getBuildVector and getSplatBuildVector helpers. NFCI.Ahmed Bougacha2016-04-2610-138/+116
| | | | | | Differential Revision: http://reviews.llvm.org/D17176 llvm-svn: 267606
* Add optimization bisect opt-in calls for Hexagon passesAndrew Kaylor2016-04-2618-1/+52
| | | | | | Differential Revision: http://reviews.llvm.org/D19509 llvm-svn: 267593
* Swift Calling Convention: use %RAX for sret.Manman Ren2016-04-263-1/+16
| | | | | | | We don't need to copy the sret argument into %rax upon return. rdar://25671494 llvm-svn: 267579
* [AMDGPU] Move reserved vgpr count for trap handler usage to ↵Konstantin Zhuravlyov2016-04-266-9/+20
| | | | | | | | SIMachineFunctionInfo + minor commenting changes Differential Revision: http://reviews.llvm.org/D19537 llvm-svn: 267573
* [AMDGPU] Reserve VGPRs for trap handler usage if instructedKonstantin Zhuravlyov2016-04-266-1/+48
| | | | | | Differential Revision: http://reviews.llvm.org/D19235 llvm-svn: 267563
* [AMDGPU] Assembler: basic support for SDWA instructionsSam Kolton2016-04-268-58/+414
| | | | | | | | | | | | | | | Support for SDWA instructions for VOP1 and VOP2 encoding. Not done yet: - converters for support optional operands and modifiers - VOPC - sext() modifier - intrinsics - VOP2b (see vop_dpp.s) - V_MAC_F32 (see vop_dpp.s) Differential Revision: http://reviews.llvm.org/D19360 llvm-svn: 267553
* [X86] PR27502: Fix the LEA optimization pass.Andrey Turetskiy2016-04-261-2/+6
| | | | | | | | Handle MachineBasicBlock as a memory displacement operand in the LEA optimization pass. Differential Revision: http://reviews.llvm.org/D19409 llvm-svn: 267551
* [Sparc] Fix build error introduced by rL267545.Marcin Koscielnicki2016-04-261-1/+1
| | | | llvm-svn: 267549
* [PowerPC] Add support for llvm.thread.pointerMarcin Koscielnicki2016-04-261-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D19304 llvm-svn: 267546
* [SPARC] [SSP] Add support for LOAD_STACK_GUARD.Marcin Koscielnicki2016-04-266-1/+40
| | | | | | | | This fixes PR22248 on sparc. Differential Revision: http://reviews.llvm.org/D19386 llvm-svn: 267545
* [SPARC] Add support for llvm.thread.pointer.Marcin Koscielnicki2016-04-262-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D19387 llvm-svn: 267544
* [ppc64] Reenable sibling call optimization on ppc64 since fixed tsan library ↵Chuang-Yu Cheng2016-04-261-1/+1
| | | | | | | | | | | tail-call issue print-stack-trace.cc test failure of compiler-rt has been fixed by r266869 (http://reviews.llvm.org/D19148), so reenable sibling call optimization on ppc64 Reviewers: nemanjai kbarton llvm-svn: 267527
* [AArch64] Expand v1i64 and v2i64 ctlz.Craig Topper2016-04-261-0/+3
| | | | | | The default is legal, which results in 'Cannot select' errors. llvm-svn: 267522
* [ARM] Expand vector ctlz_zero_undef so it becomes ctlz.Craig Topper2016-04-261-0/+10
| | | | | | The default is Legal, which results in 'Cannot select' errors. llvm-svn: 267521
* [ARM] Expand v1i64 and v2i64 ctlz.Craig Topper2016-04-261-0/+3
| | | | | | The default is legal, which results in 'Cannot select' errors. llvm-svn: 267520
* [WebAssembly] Account for implicit operands when computing operand indices.Dan Gohman2016-04-261-1/+1
| | | | llvm-svn: 267511
* Reverting Thumb2SizeReduction opt bisect change to fix failing buildbots.Andrew Kaylor2016-04-261-2/+1
| | | | llvm-svn: 267506
* Remove MinLatency in SchedMachineModel. NFC.Junmo Park2016-04-2611-14/+0
| | | | | | | | | | | Summary: We don't use MinLatency any more since r184032. Reviewers: atrick, hfinkel, mcrosier Differential Revision: http://reviews.llvm.org/D19474 llvm-svn: 267502
* [X86] Use LivePhysRegs in X86FixupBWInsts.Ahmed Bougacha2016-04-261-13/+19
| | | | | | | | | Kill-flags, which computeRegisterLiveness uses, are not reliable. LivePhysRegs is. Differential Revision: http://reviews.llvm.org/D19472 llvm-svn: 267495
* [Sparc] Fix double-float fabs and fneg on little endian CPUs.James Y Knight2016-04-251-12/+28
| | | | | | | | | | | | | | | | The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
* Fix build warningAndrew Kaylor2016-04-251-1/+1
| | | | llvm-svn: 267487
* Add optimization bisect opt-in calls for AMDGPU passesAndrew Kaylor2016-04-257-1/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D19450 llvm-svn: 267485
* Add optimization bisect opt-in calls for ARM passesAndrew Kaylor2016-04-255-2/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D19449 llvm-svn: 267480
* Add optimization bisect opt-in calls for AArch64 passesAndrew Kaylor2016-04-2512-0/+34
| | | | | | Differential Revision: http://reviews.llvm.org/D19394 llvm-svn: 267479
* ARM: put extern __thread stubs in a special section.Tim Northover2016-04-251-2/+18
| | | | | | | The linker needs to know that the symbols are thread-local to do its job properly. llvm-svn: 267473
* [Hexagon] Few fixes for exception handlingKrzysztof Parzyszek2016-04-252-1/+2
| | | | llvm-svn: 267469
* Re-apply r267206 with a fix for the encoding problem: when the immediate ofQuentin Colombet2016-04-251-3/+14
| | | | | | | | | | | | | | | | | | log2(Mask) is smaller than 32, we must use the 32-bit variant because the 64-bit variant cannot encode it. Therefore, set the subreg part accordingly. [AArch64] Fix optimizeCondBranch logic. The opcode for the optimized branch does not depend on the size of the activate bits in the AND masks, but the AND opcode itself. Indeed, we need to use a X or W variant based on the AND variant not based on whether the mask fits into the related variant. Otherwise, we may end up using the W variant of the optimized branch for 64-bit register inputs! This fixes the last make check verifier issues for AArch64: PR27479. llvm-svn: 267465
* AMDGPU/SI: Optimize adjacent s_nop instructionsMatt Arsenault2016-04-251-0/+27
| | | | | | | | | | | | Use the operand for how long to wait. This is somewhat distasteful, since it would be better to just emit s_nop with the right argument in the first place. This would require changing TII::insertNoop to emit N operands, which would be easy. Slightly more problematic is the post-RA scheduler and hazard recognizer represent nops as a single null node, and would require inventing another way of representing N nops. llvm-svn: 267456
* AMDGPU: Implement addrspacecastMatt Arsenault2016-04-255-71/+124
| | | | llvm-svn: 267452
* AMDGPU: Add queue ptr intrinsicMatt Arsenault2016-04-254-3/+18
| | | | llvm-svn: 267451
* AMDGPU: Add DAG to debug dumpMatt Arsenault2016-04-251-2/+2
| | | | | | Also reorder case to match enum order llvm-svn: 267449
* [Hexagon] Register save/restore functions do not follow regular conventionsKrzysztof Parzyszek2016-04-254-45/+51
| | | | | | Do not mark them as modifying any of the volatile registers by default. llvm-svn: 267433
* [lanai] Expand findClosestSuitableAluInstr check to consider offset register.Jacques Pienaar2016-04-251-3/+6
| | | | | | Previously findClosestSuitableAluInstr was only considering the base register when checking the current instruction for suitability. Expand check to consider the offset if the offset is a register. llvm-svn: 267424
* [mips][microMIPS] Revert commit r267137Hrvoje Varga2016-04-254-14/+3
| | | | | | Commit r267137 was the reason for failing tests in LLVM test suite. llvm-svn: 267419
* [mips][microMIPS] Revert commit r266977Zlatko Buljan2016-04-254-26/+9
| | | | | | Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ... llvm-svn: 267418
OpenPOWER on IntegriCloud