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author | Marcin Koscielnicki <koriakin@0x04.net> | 2016-04-26 10:37:22 +0000 |
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committer | Marcin Koscielnicki <koriakin@0x04.net> | 2016-04-26 10:37:22 +0000 |
commit | 0cfb612413f48f1e0d394b96ef5ac2c127a150c1 (patch) | |
tree | a27c43bf14e68fbb8d59cd7bc5092882b2fde985 /llvm/lib/Target | |
parent | 33571e2c415cc4d6f2375a6499278110a65da1b7 (diff) | |
download | bcm5719-llvm-0cfb612413f48f1e0d394b96ef5ac2c127a150c1.tar.gz bcm5719-llvm-0cfb612413f48f1e0d394b96ef5ac2c127a150c1.zip |
[PowerPC] Add support for llvm.thread.pointer
Differential Revision: http://reviews.llvm.org/D19304
llvm-svn: 267546
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 72335a4f999..15efeb8cc9d 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -7715,6 +7715,16 @@ static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc, /// lower, do it, otherwise return null. SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { + unsigned IntrinsicID = + cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); + + if (IntrinsicID == Intrinsic::thread_pointer) { + // Reads the thread pointer register, used for __builtin_thread_pointer. + bool is64bit = Subtarget.isPPC64(); + return DAG.getRegister(is64bit ? PPC::X13 : PPC::R2, + is64bit ? MVT::i64 : MVT::i32); + } + // If this is a lowered altivec predicate compare, CompareOpc is set to the // opcode number of the comparison. SDLoc dl(Op); |