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* [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fddAlexander Timofeev2019-06-064-163/+107
* [X86] Make a bunch of merge masked binops commutable for loading folding.Craig Topper2019-06-061-8/+7
* [AIX] Implement function descriptor on SDAGJason Liu2019-06-064-18/+64
* Remove unused PPC.h includes under llvm/lib/Target/PowerPC.Dmitri Gribenko2019-06-063-4/+1
* [X86] Make masked floating point equality/ordered compares commutable for loa...Craig Topper2019-06-062-7/+17
* [AIX] Implement call lowering with parameters could pass onto GPRsJason Liu2019-06-062-15/+83
* AArch64] Handle ISD::LRINT and ISD::LLRINT for float16Adhemerval Zanella2019-06-061-0/+8
* [AArch64] Handle ISD::LROUND and ISD::LLROUND for float16Adhemerval Zanella2019-06-061-0/+8
* Include what you use in LanaiAsmParser.cppDmitri Gribenko2019-06-061-1/+0
* [MIPS GlobalISel] Select sqrtPetar Avramovic2019-06-062-2/+3
* [MIPS GlobalISel] Select fabsPetar Avramovic2019-06-063-2/+13
* [MIPS GlobalISel] Select fpext and fptruncPetar Avramovic2019-06-062-0/+14
* [MIPS GlobalISel] Select floor and ceilPetar Avramovic2019-06-061-0/+3
* [AArch64][GlobalISel] Add manual selection support for G_ZEXTLOADs to s64.Amara Emerson2019-06-061-0/+23
* [AArch64][GlobalISel] Add the new changes to fix PR42129 that were supposed t...Amara Emerson2019-06-061-0/+5
* [X86] Don't turn avx masked.load with constant mask into masked.load+vselect ...Craig Topper2019-06-061-0/+3
* Revert "Revert "[AArch64][GlobalISel] Optimize G_FCMP + G_SELECT pairs when G...Amara Emerson2019-06-051-8/+96
* AMDGPU: Don't fix emergency stack slot at offset 0Matt Arsenault2019-06-052-26/+11
* Allow target to handle STRICT floating-point nodesUlrich Weigand2019-06-054-188/+251
* Revert "[AArch64][GlobalISel] Optimize G_FCMP + G_SELECT pairs when G_SELECT ...Petr Hosek2019-06-051-96/+8
* AMDGPU: Invert frame index offset interpretationMatt Arsenault2019-06-059-209/+218
* [X86] Fix mistake that marked VADDSSrrb_Int/VADDSDrrb_Int/VMULSSrrb_Int/VMULS...Craig Topper2019-06-051-1/+1
* AMDGPU: Remove amdgpu-max-work-group-size attributeMatt Arsenault2019-06-051-10/+1
* AMDGPU: Fix using 2 different enums for same operand flagsMatt Arsenault2019-06-053-11/+8
* [WebAssembly] Limit PIC support to the Emscripten targetDan Gohman2019-06-051-2/+11
* [X86] Add the vector integer min/max instructions to isAssociativeAndCommutat...Craig Topper2019-06-051-0/+84
* [x86] split more 256-bit stores of concatenated vectorsSanjay Patel2019-06-051-3/+4
* [X86][AVX] Generalize split256BitStore to splitVectorStore. NFCI.Simon Pilgrim2019-06-051-12/+17
* [MIPS GlobalISel] Select fcmpPetar Avramovic2019-06-053-0/+94
* [X86][AVX] combineX86ShuffleChain - combine shuffle(extractsubvector(x),extra...Simon Pilgrim2019-06-051-3/+10
* Include what you use in PPCFrameLowering.hDmitri Gribenko2019-06-051-1/+0
* [PowerPC] Collapse RLDICL/RLDICR into RLDIC when possibleNemanja Ivanovic2019-06-051-0/+52
* [X86] Cleanup convertIntLogicToFPLogic a little. NFCICraig Topper2019-06-051-23/+24
* [AArch64][GlobalISel] Make extloads to i64 legal.Amara Emerson2019-06-041-0/+3
* [WebAssembly] Fix ISel crash on sext_inreg/extract type mismatchThomas Lively2019-06-041-2/+26
* [X86] Mutate fceil/ffloor/ftrunc/fnearbyint/frint into X86ISD::RNDSCALE durin...Craig Topper2019-06-043-357/+82
* [X86] Fold single-use variable into assert. NFC.Benjamin Kramer2019-06-041-2/+2
* [x86] split 256-bit store of concatenated vectorsSanjay Patel2019-06-041-0/+11
* [AArch64][ELF] Add support for PLT decoding with BTI instructions presentPeter Smith2019-06-041-1/+9
* [PowerPC] P9 Scheduling Model: dispatching rule fixesJinsong Ji2019-06-042-126/+162
* [SelectionDAG][x86] limit post-legalization store merging by typeSanjay Patel2019-06-042-2/+6
* [X86][SSE] Pulled out (sub (xor X, M), M) 'ConditionalNegate' out pattern mat...Simon Pilgrim2019-06-041-49/+66
* [Support] make countLeadingZeros() countTrailingZeros() countLeadingOnes() an...Shawn Landden2019-06-041-1/+1
* Include what you use in PPCRegisterInfo.cppDmitri Gribenko2019-06-041-1/+0
* [ARM] Add FP16 vector insert/extract patternsMikhail Maltsev2019-06-041-0/+53
* Include what you use in PPC.hDmitri Gribenko2019-06-041-1/+0
* Include what you use in PPCMachineScheduler.cppDmitri Gribenko2019-06-041-1/+3
* Include what you use in PPCRegisterInfo.hDmitri Gribenko2019-06-041-1/+2
* [ARM] Turn some undefined encoding bits into 0s.Simon Tatham2019-06-041-0/+17
* AMDGPU: Disable stack realignment for kernelsMatt Arsenault2019-06-032-0/+14
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