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* add a copy ctor to TargetLibraryInfo.Chris Lattner2011-05-211-0/+6
| | | | llvm-svn: 131806
* X86: smulo -> add is now done target-independently in DAGCombiner, remove ↵Benjamin Kramer2011-05-211-6/+0
| | | | | | the patterns. llvm-svn: 131801
* Fix PR9978 by adding RIP to GR64_TC so it can be used as an address in PIC ↵Cameron Zwarich2011-05-211-1/+1
| | | | | | | | | code. It is already in GR64 for the same reasons. Since it isn't allocatable it can't cause any problems. llvm-svn: 131787
* Use the correct register to access stack frame objects.Akira Hatanaka2011-05-211-10/+31
| | | | llvm-svn: 131785
* Insert instructions that copy $sp to or from $fp at the right locations. Akira Hatanaka2011-05-211-11/+26
| | | | llvm-svn: 131784
* Change the order fixed objects are created in MipsTargetLowering::LowerCall inAkira Hatanaka2011-05-201-25/+35
| | | | | | | | | | | | | | preparation for reversing StackDirection. Fixed objects are created in the following order: 1. Incoming arguments passed on stack. 2. va_arg objects (include both arguments that are passed in registers and pointer to the location of the first va_arg argument). 3. $gp restore slot. 4. Outgoing arguments passed on stack. 5. Pointer to alloca'd space. llvm-svn: 131767
* Add fast-isel support for byval calls on x86.Eli Friedman2011-05-201-17/+51
| | | | llvm-svn: 131764
* In CC_MipsO32, allocate a stack space regardless of whether the argument isAkira Hatanaka2011-05-201-22/+25
| | | | | | passed in register or on the stack. llvm-svn: 131758
* Define functions that get/set maximum call frame size.Akira Hatanaka2011-05-201-1/+6
| | | | llvm-svn: 131752
* adds some attributes to attribute section when cpu is "xscale"Rafael Espindola2011-05-201-0/+6
| | | | | | | | (this is what used in Android NDK, when architecture is ARMv5) patch by Koan-Sin Tan llvm-svn: 131751
* fixes target address tBL and tBLX and sets relocation typeRafael Espindola2011-05-201-2/+2
| | | | | | | | of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6) Patch by koan-sin tan. llvm-svn: 131748
* Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.Stuart Hastings2011-05-205-50/+38
| | | | | | rdar://problem/8614450 llvm-svn: 131746
* Make $fp and $ra callee-saved registers and let PrologEpilogInserter handleAkira Hatanaka2011-05-205-101/+37
| | | | | | saving and restoring them. llvm-svn: 131745
* Revert accidental commit.Evan Cheng2011-05-203-10/+1
| | | | llvm-svn: 131739
* Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility.Benjamin Kramer2011-05-201-1/+1
| | | | llvm-svn: 131730
* Remove noisy semicolons.Benjamin Kramer2011-05-201-1/+1
| | | | llvm-svn: 131724
* Fix bug in which nodes that write to argument registers do not get glued ↵Akira Hatanaka2011-05-201-11/+12
| | | | | | with the JALR node. Patch by Sasa Stankovic llvm-svn: 131714
* Remove code that creates unnecessary frame objects.Akira Hatanaka2011-05-201-4/+0
| | | | llvm-svn: 131711
* Define variables and functions in MipsFunctionInfo.Akira Hatanaka2011-05-201-1/+30
| | | | | | | This is the first of a series of patches that attempt to simplify handling of stack frame objects. llvm-svn: 131710
* Don't attempt to tail call optimize for Win64.Chad Rosier2011-05-201-6/+7
| | | | llvm-svn: 131709
* Revert r131664 and fix it in instcombine instead. rdar://9467055Evan Cheng2011-05-204-14/+10
| | | | llvm-svn: 131708
* Add fast-isel support for zeroext and signext ret instructions on x86.Eli Friedman2011-05-191-5/+25
| | | | llvm-svn: 131689
* Oddly people want to use the 'r' constraint for fp constants on x86.Eric Christopher2011-05-191-1/+1
| | | | | | | Fixes rdar://9218925 Fixes PR9601 llvm-svn: 131682
* This fixes one divergence between LLVM and binutils for ARM in theJason W Kim2011-05-191-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | text section. Assume the following bit of annotated assembly: .section .data.rel.ro,"aw",%progbits .align 2 .LAlpha: .long startval(GOTOFF) .text .align 2 .type main,%function .align 4 main: ;;; assume "main" starts at offset 0x20 0x0 push {r11, lr} 0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8)) ;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8) ;;; ==> (??? - ((16-4) + 8) = -20 0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8)) ;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8) ;;; ==> (??? - ((16-8) + 8) = -16 0xc ... blah .LBeta: 0x10 add r0, pc, r0 0x14 ... blah .LGamma: 0x18 add r1, pc, r1 Above snippet results in the following relocs in the .o file for the first pair of movw/movt instructions 00000024 R_ARM_MOVW_PREL_NC .LAlpha 00000028 R_ARM_MOVT_PREL .LAlpha And the encoded instructions in the .o file for main: must be 00000020 <main>: 20: e92d4800 push {fp, lr} 24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20 28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16 However, llc (prior to this commit) generates the following sequence 00000020 <main>: 20: e92d4800 push {fp, lr} 24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20 28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1 What has to happen in the ArmAsmBackend is that if the relocation is PC relative, the 16 bits encoded as part of movw and movt must be both addends, not addresses. It makes sense to encode addresses by right shifting the value by 16, but the result is incorrect for PIC. i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case. This change agrees with what GNU as does, and makes the PIC code run. MC/ARM/elf-movt.s covers this case. llvm-svn: 131674
* ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.Rafael Espindola2011-05-191-1/+2
| | | | | | | | Fixes PR9934. We really need to start tblgening the relocation info :-( llvm-svn: 131669
* Align i64 arguments to 64 bit boundaries.Akira Hatanaka2011-05-191-1/+7
| | | | llvm-svn: 131668
* crc32 with 64-bit output zeros upper 32-bits. rdar://9467055Evan Cheng2011-05-191-0/+13
| | | | llvm-svn: 131664
* Increase number of available registers when target is MIPS32.Akira Hatanaka2011-05-192-3/+11
| | | | llvm-svn: 131660
* Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa ↵Akira Hatanaka2011-05-191-90/+28
| | | | | | Stankovic. llvm-svn: 131657
* Reverting 131641 to investigate 'bot complaint.Stuart Hastings2011-05-193-21/+25
| | | | llvm-svn: 131654
* 80 columns.Jim Grosbach2011-05-191-9/+12
| | | | llvm-svn: 131649
* Fix data layout string. i64 is aligned to 64 bit boundaries.Akira Hatanaka2011-05-191-2/+3
| | | | llvm-svn: 131642
* Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer beStuart Hastings2011-05-193-25/+21
| | | | | | pseudos. rdar://problem/8614450 llvm-svn: 131641
* Use the correct register class for Cell varargs spilling. This fixes all of theCameron Zwarich2011-05-191-1/+1
| | | | | | verifier failures in the CodeGen/CellSPU tests. llvm-svn: 131631
* Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for ↵Mon P Wang2011-05-191-7/+7
| | | | | | this change. llvm-svn: 131630
* Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier.Cameron Zwarich2011-05-191-1/+2
| | | | llvm-svn: 131627
* Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointlessCameron Zwarich2011-05-193-5/+4
| | | | | | | | piclabel operand. The operand in the tablegen definition doesn't actually turn into an MI operand, so it just confuses anything checking the TargetInstrDesc for the number of operands. It suffices to just have an implicit def of LR. llvm-svn: 131626
* Reuse the TargetInstrDesc.Cameron Zwarich2011-05-191-2/+1
| | | | llvm-svn: 131625
* Correctly constrain a register class when computing frame offsets, as the Thumb2Cameron Zwarich2011-05-191-0/+4
| | | | | | add instruction takes an rGPR. This fixes the last of PR8825. llvm-svn: 131619
* Revert unintentional commit.Eli Friedman2011-05-181-26/+5
| | | | llvm-svn: 131597
* More instcombine simplifications towards better debug locations.Eli Friedman2011-05-181-5/+26
| | | | llvm-svn: 131596
* Add missing mayLoad / mayStore flags to instruction definitions without ↵Cameron Zwarich2011-05-181-0/+5
| | | | | | | | patterns, which fixes all of the CodeGen/MBlaze verifier failures. llvm-svn: 131595
* Reserve the segment registers on x86 to fix verifier failures in any code thatCameron Zwarich2011-05-181-0/+9
| | | | | | uses them. llvm-svn: 131591
* Reserve r29 on Alpha. This fixes all verifier failures in CodeGen/Alpha.Cameron Zwarich2011-05-181-0/+1
| | | | llvm-svn: 131587
* Handle perfect shuffle case that generates a vrev for vectors of floats.Tanya Lattner2011-05-181-1/+2
| | | | | | Add test case. llvm-svn: 131582
* Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing ↵Cameron Zwarich2011-05-181-4/+7
| | | | | | turned on. llvm-svn: 131578
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' ↵Johnny Chen2011-05-181-1/+1
| | | | | | immediate operand. llvm-svn: 131565
* Enables vararg functions that pass all arguments via registers to be ↵Chad Rosier2011-05-181-5/+18
| | | | | | optimized into tail-calls when possible. llvm-svn: 131560
* Revise r131553. Just use the type of the input node and forgo the bitcast. ↵Evan Cheng2011-05-181-4/+3
| | | | | | rdar://9449159. llvm-svn: 131555
* Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same ↵Evan Cheng2011-05-181-1/+3
| | | | | | type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 llvm-svn: 131553
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