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* yet more aliases.Chris Lattner2010-09-271-0/+3
| | | | llvm-svn: 114822
* add a couple more aliases, rdar://8456378Chris Lattner2010-09-271-0/+2
| | | | llvm-svn: 114821
* fix rdar://8470918 - llvm-mc can't assemble smovlChris Lattner2010-09-271-0/+4
| | | | llvm-svn: 114819
* Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands.Chris Lattner2010-09-271-5/+4
| | | | | | | | My previous fix for rdar://8456371 should only apply to fmulp/faddp, not to fmul/fadd. Instruction set orthogonality is overrated or something. llvm-svn: 114818
* the latest assembler that runs on powerpc 10.4 machines doesn'tChris Lattner2010-09-271-0/+1
| | | | | | | support aligned comm. Detect when compiling for 10.4 and don't emit an alignment for comm. THis will hopefully fix PR8198. llvm-svn: 114817
* improve indentationChris Lattner2010-09-271-3/+3
| | | | llvm-svn: 114815
* Insert missing coherency in comment. Add a quick check for hardwareEric Christopher2010-09-271-3/+7
| | | | | | divide support also. llvm-svn: 114813
* Mass rename for Jim.Eric Christopher2010-09-271-33/+33
| | | | llvm-svn: 114812
* This code should never fire on non-darwin subtargets.Eric Christopher2010-09-271-3/+3
| | | | llvm-svn: 114811
* implement support for 'clr' alias. This is part of rdar://8416805,Chris Lattner2010-09-271-0/+11
| | | | | | but balrog was wanting it on irc. llvm-svn: 114809
* Add ret instruction to PTX backendChe-Liang Chiou2010-09-253-2/+27
| | | | llvm-svn: 114788
* Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to putRafael Espindola2010-09-251-0/+6
| | | | | | symbols defined in merge sections in independent atoms. llvm-svn: 114786
* Fix IIC_iEXTAr itinerary class of Cortex-A9.Evan Cheng2010-09-251-1/+1
| | | | llvm-svn: 114784
* Remove a unused instruction itinerary class.Evan Cheng2010-09-254-4/+0
| | | | llvm-svn: 114782
* Fix zero and sign extension instructions scheduling itineraries.Evan Cheng2010-09-255-31/+45
| | | | llvm-svn: 114780
* More pseudo instruction scheduling itinerary fixes.Evan Cheng2010-09-245-3/+25
| | | | llvm-svn: 114768
* Fix scheduling itinerary for pseudo mov immediate instructions which expand ↵Evan Cheng2010-09-245-5/+12
| | | | | | into two real instructions. llvm-svn: 114766
* Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.Jim Grosbach2010-09-241-0/+95
| | | | llvm-svn: 114758
* Enable code placement optimization pass for ARM.Evan Cheng2010-09-241-7/+1
| | | | llvm-svn: 114746
* We can't return SSE/MMX vectors if SSE is disabled.Dale Johannesen2010-09-241-3/+5
| | | | llvm-svn: 114745
* Fix a potential null dereference bug.Evan Cheng2010-09-241-4/+12
| | | | llvm-svn: 114723
* Revert r114703 and r114702, removing the isConditionalMove flag from ↵Owen Anderson2010-09-235-10/+10
| | | | | | | | instructions. After further reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board! llvm-svn: 114710
* Set alignment operand for NEON VST instructions.Bob Wilson2010-09-231-14/+22
| | | | llvm-svn: 114709
* ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansionJim Grosbach2010-09-231-0/+77
| | | | llvm-svn: 114707
* #+4 --> #4 for consistency with other asm outputJim Grosbach2010-09-231-2/+2
| | | | llvm-svn: 114706
* Fix formatting of output .s codeJim Grosbach2010-09-231-1/+1
| | | | llvm-svn: 114705
* Add isConditionalMove bits to X86 and ARM instructions.Owen Anderson2010-09-235-10/+10
| | | | llvm-svn: 114703
* Set alignment operand for NEON VLD instructions.Bob Wilson2010-09-231-0/+16
| | | | llvm-svn: 114696
* never mind. I can't read, apparentlyJim Grosbach2010-09-231-1/+1
| | | | llvm-svn: 114689
* Fix r114632. Return if the only terminator is an unconditional branch after ↵Evan Cheng2010-09-231-3/+5
| | | | | | the redundant ones are deleted. llvm-svn: 114688
* Fix opcode value for the 'trap' instruction, keeping the type suffix on theJim Grosbach2010-09-231-1/+1
| | | | | | constant. Hopefully the non-Darwin bots will like it... llvm-svn: 114687
* explicit 'unsigned long' on constant value. Hopefully make bots happier.Jim Grosbach2010-09-231-1/+1
| | | | llvm-svn: 114686
* Unbreak build. Jim, please review.Benjamin Kramer2010-09-231-4/+4
| | | | llvm-svn: 114684
* Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don'tJim Grosbach2010-09-233-6/+36
| | | | | | | | | | | | (yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the opcode directly. On Darwin, however, we do want the mnemonic for more readable assembly code and better disassembly. Adjust the .td file to use the 'trap' mnemonic and handle using the binutils workaround in the assembly printer. Also tweak the formatting of the opcode values to make them consistent between the MC printer and the old printer. llvm-svn: 114679
* nuke unused varJim Grosbach2010-09-231-1/+0
| | | | llvm-svn: 114676
* If there are multiple unconditional branches terminating a block, eliminate allEvan Cheng2010-09-231-1/+17
| | | | | | | but the first one. Those will never be executed. There was logic to do this but it was faulty. llvm-svn: 114632
* Add support for ELF PLT references for ARM MC asm printing. Adding aJim Grosbach2010-09-224-15/+45
| | | | | | | | new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure there's a more straightforward way to get the printing difference captured. (i.e., x86 uses @PLT, ARM uses (PLT)). llvm-svn: 114613
* Enable a few additional asserts in MC instruction lowering.Jim Grosbach2010-09-221-9/+6
| | | | llvm-svn: 114601
* Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.Cameron Esfahani2010-09-221-2/+3
| | | | llvm-svn: 114597
* Change VDUPLANE DAG combiner to just return the result instead of callingBob Wilson2010-09-221-5/+3
| | | | | | | | CombineTo to avoid putting the result on the worklist. I don't think it makes much difference for now, but it might help someday as we add more DAG combine optimizations. llvm-svn: 114595
* Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing oneBob Wilson2010-09-221-28/+35
| | | | | | | | of those. Refactor to share code for handling BUILD_VECTOR(VMOVRRD). I don't have a testcase that exercises this, but it seems like an obvious good thing to do. llvm-svn: 114589
* add FIXMEJim Grosbach2010-09-221-0/+1
| | | | llvm-svn: 114578
* Temporarily work around new address lowering while I figure out whatEric Christopher2010-09-221-1/+2
| | | | | | needs to happen for darwin. llvm-svn: 114577
* Remove a few commented out bitsJim Grosbach2010-09-221-14/+0
| | | | llvm-svn: 114576
* Add PrintSpecial() handling for in ARM MC instruction printer.Jim Grosbach2010-09-222-2/+9
| | | | llvm-svn: 114563
* Add MC instruction printer support for ARM and Thumb1 jump tables.Jim Grosbach2010-09-221-3/+49
| | | | llvm-svn: 114555
* Attempt to fix llvm-gcc build. It was crashing when building gcov.o for anBob Wilson2010-09-221-2/+3
| | | | | | | | ARM cross-compiler on x86, because the MMO size did not match the type size. This fixes the MMO size and also the size of the stack object to match the type size. llvm-svn: 114554
* Add MC instruction printer support for TB[BH] style thumb2 jump tables.Jim Grosbach2010-09-221-24/+27
| | | | llvm-svn: 114553
* Clean up comment.Jim Grosbach2010-09-221-4/+4
| | | | llvm-svn: 114550
* fix rdar://8456371 - Handle commutable instructions written backward.Chris Lattner2010-09-221-0/+10
| | | | llvm-svn: 114536
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