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| author | Evan Cheng <evan.cheng@apple.com> | 2010-09-25 01:06:02 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-09-25 01:06:02 +0000 |
| commit | 8f9a2244fc55de8114fde15fc8e9411864e089a1 (patch) | |
| tree | 8e230324a040a211be4a2ea063c6dc4d641c1c78 /llvm/lib/Target | |
| parent | ebacd2b023e1071511bc6a24d4db718478ac5bcb (diff) | |
| download | bcm5719-llvm-8f9a2244fc55de8114fde15fc8e9411864e089a1.tar.gz bcm5719-llvm-8f9a2244fc55de8114fde15fc8e9411864e089a1.zip | |
Remove a unused instruction itinerary class.
llvm-svn: 114782
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSchedule.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA8.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA9.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleV6.td | 1 |
4 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMSchedule.td b/llvm/lib/Target/ARM/ARMSchedule.td index 06a5f30f004..c64c4392a3b 100644 --- a/llvm/lib/Target/ARM/ARMSchedule.td +++ b/llvm/lib/Target/ARM/ARMSchedule.td @@ -17,7 +17,6 @@ def IIC_iALUsi : InstrItinClass; def IIC_iALUsr : InstrItinClass; def IIC_iUNAr : InstrItinClass; def IIC_iUNAsi : InstrItinClass; -def IIC_iUNAsr : InstrItinClass; def IIC_iEXTr : InstrItinClass; def IIC_iEXTAr : InstrItinClass; def IIC_iCMPi : InstrItinClass; diff --git a/llvm/lib/Target/ARM/ARMScheduleA8.td b/llvm/lib/Target/ARM/ARMScheduleA8.td index 48d1905aeef..864ada01629 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA8.td +++ b/llvm/lib/Target/ARM/ARMScheduleA8.td @@ -40,7 +40,6 @@ def CortexA8Itineraries : ProcessorItineraries< // Unary Instructions that produce a result InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, - InstrItinData<IIC_iUNAsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, // // Zero and sign extension instructions InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td index 6d547295ea6..4118b90907d 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA9.td +++ b/llvm/lib/Target/ARM/ARMScheduleA9.td @@ -50,7 +50,6 @@ def CortexA9Itineraries : ProcessorItineraries< // Unary Instructions that produce a result InstrItinData<IIC_iUNAr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>, InstrItinData<IIC_iUNAsi , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 1]>, - InstrItinData<IIC_iUNAsr , [InstrStage<3, [A9_Pipe0, A9_Pipe1]>], [2, 1, 1]>, // // Zero and sign extension instructions InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>, diff --git a/llvm/lib/Target/ARM/ARMScheduleV6.td b/llvm/lib/Target/ARM/ARMScheduleV6.td index efead927144..866e2e1e237 100644 --- a/llvm/lib/Target/ARM/ARMScheduleV6.td +++ b/llvm/lib/Target/ARM/ARMScheduleV6.td @@ -33,7 +33,6 @@ def ARMV6Itineraries : ProcessorItineraries< // Unary Instructions that produce a result InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, InstrItinData<IIC_iUNAsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, - InstrItinData<IIC_iUNAsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, // // Zero and sign extension instructions InstrItinData<IIC_iEXTr , [InstrStage<1, [V6_Pipe]>], [1, 1]>, |
