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* [X86][BtVer2] Cleanup some old FIXMEs from the model. NFCI.Simon Pilgrim2018-04-201-5/+2
| | | | llvm-svn: 330428
* [X86] Tag CLDEMOTE instruction with WriteLoad scheduling classSimon Pilgrim2018-04-201-1/+2
| | | | | | Same as other cacheline instructions llvm-svn: 330424
* [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load ↵Sander de Smalen2018-04-203-2/+53
| | | | | | | | | | | | | | | | | | | instructions. This is patch [4/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45690 llvm-svn: 330423
* [AArch64][SVE] Fix diagnostic for SVE LD4 instructions:Sander de Smalen2018-04-201-1/+1
| | | | | | | | | | Diagnostic: 'index must be multiple of 3 in range [-32, 28]' Must be: 'index must be multiple of 4 in range [-32, 28]' llvm-svn: 330407
* [AArch64][SVE] Added GPR64shifted and GPR64NoXZRshifted register classes.Sander de Smalen2018-04-205-7/+88
| | | | | | | | | | | | | | | | | | | | Summary: This is patch [3/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: SjoerdMeijer Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45689 llvm-svn: 330406
* Revert "This pass, fixing an erratum in some LEON 2 processors..."Daniel Cederman2018-04-205-18/+1
| | | | | | | | | | | | | | | | | | | | | Summary: Reading Atmel's AT697E errata document this does not seem like a valid workaround. While the text only mentions SDIV, it says that the ICC flags can be wrong, and those are only generated by SDIVcc. Verification on hardware shows that simply replacing SDIV with SDIVcc does not avoid the bug with negative operands. This reverts r283727. Reviewers: lero_chris, jyknight Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45813 llvm-svn: 330397
* [Sparc] Use synthetic instruction clr to zero register instead of sethiDaniel Cederman2018-04-201-0/+3
| | | | | | | | | | | | | | | Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register looks much better than `sethi 0, reg`. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45810 llvm-svn: 330396
* [AArch64][AsmParser] Extend RegOp with integrated 'shift/extend'.Sander de Smalen2018-04-202-36/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In some cases the shift/extend needs to be explicitly parsed together with the register, rather than as a separate operand. This is needed for addressing modes where the instruction as a whole dictates the scaling/extend, rather than specific bits in the instruction. By parsing them as a single operand, we avoid the need to pass an extra operand in all CodeGen patterns (because all operands need to have an associated value), and we avoid the need to update TableGen to accept operands that have no associated bits in the instruction. An added benefit of parsing them together is that the assembler can give a sensible diagnostic if the scaling is not correct. This is patch [2/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: fhahn, SjoerdMeijer Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45688 llvm-svn: 330394
* AMDGPU: Legalize the operand of SI_INIT_M0Nicolai Haehnle2018-04-201-0/+15
| | | | | | | | | | | | | | | | | | | | Summary: This fixes a case where the argument to a sendmsg intrinsic ends up in a VGPR, for whatever reason. The underlying performance issue is that a multiplication that can be an s_mul_i32 is instead needlessly generated as v_mul_u32_u24, but this is not addressed by this patch. Change-Id: I61fd4034314d5acdf6074632c30b65364dfa7328 Reviewers: arsenm, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45826 llvm-svn: 330393
* [Sparc] Fix addressing mode when using 64-bit values in inline assemblyDaniel Cederman2018-04-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If a 64-bit register is used as an operand in inline assembly together with a memory reference, the memory addressing will be wrong. The addressing will be a single reg, instead of reg+reg or reg+imm. This will generate a bad offset value or an exception in printMemOperand(). For example: ``` long long int val = 5; long long int mem; __asm__ volatile ("std %1, %0":"=m"(mem):"r"(val)); ``` becomes: ``` std %i0, [%i2+589833] ``` The problem is that SelectInlineAsmMemoryOperand() is never called for the memory references if one of the operands is a 64-bit register. By calling SelectInlineAsmMemoryOperands() in tryInlineAsm() the Sparc version of SelectInlineAsmMemoryOperand() gets called for each memory reference. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45761 llvm-svn: 330392
* [AMDGPU] Use packed literals with zero either lower or hi partStanislav Mekhanoshin2018-04-192-2/+21
| | | | | | Differential Revision: https://reviews.llvm.org/D45790 llvm-svn: 330365
* [X86] Enable popcnt false dependency breaking on Silvermont and Goldmont.Craig Topper2018-04-191-2/+6
| | | | | | Silvermont and Goldmont have the same issue on popcnt as Sandy Bridge, Haswell, Broadwell, and Skylake. Believe it is fixed in Goldmont Plus. llvm-svn: 330358
* [X86][SLM] Fix typo using SandyBridge resources. Simon Pilgrim2018-04-191-2/+2
| | | | | | Luckily this was on instructions not supported on Silvermont.... llvm-svn: 330351
* [X86] Correct the scheduling data for register forms of XCHG and XADD on ↵Craig Topper2018-04-195-22/+24
| | | | | | | | | | | | Intel CPUs. The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register. XADD is probably 2 moves and an add also using a temporary register. Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available. llvm-svn: 330349
* [X86] Merge some MMX instregexSimon Pilgrim2018-04-195-269/+88
| | | | | | There's a lot more but I'd prefer focussing on removing unnecessary InstRWs first. llvm-svn: 330347
* [Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTORKrzysztof Parzyszek2018-04-191-0/+26
| | | | llvm-svn: 330344
* [AMDGPU] Do not only rely on BB number when finding bottom loopMark Searles2018-04-191-20/+45
| | | | | | | | We should also check that the "bottom" basic block of a loopis a successor of the "header" basic block, otherwise we don't propagate the information correctly when the CFG is complex. This fixes an important rendering problem with Wolfsentein 2, because of one vector-memory wait was missing. Differential Revision: https://reviews.llvm.org/D43831 llvm-svn: 330337
* [Hexagon] Generate code for vector bswap intrinsicsKrzysztof Parzyszek2018-04-191-0/+5
| | | | llvm-svn: 330333
* [X86][BtVer2] Remove SSE4A EXTRQ/EXTRQI InstRW overrides.Simon Pilgrim2018-04-191-4/+0
| | | | | | These are already handled identically by WriteALU. llvm-svn: 330332
* [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical opsKrzysztof Parzyszek2018-04-192-99/+89
| | | | llvm-svn: 330330
* [mips] Correct the definitions of the unaligned word memory operation ↵Simon Dardis2018-04-194-25/+40
| | | | | | | | | | | | | | | | instructions These instructions lacked the correct predicates, were not marked as loads and stores and lacked the proper instruction mapping information. In the case of microMIPS sw(l|r)e (EVA) these instructions were using the load EVA description. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45626 llvm-svn: 330326
* Lowering x86 adds/addus/subs/subus intrinsics (llvm part)Alexander Ivchenko2018-04-192-40/+89
| | | | | | | | | | | | | This is the patch that lowers x86 intrinsics to native IR in order to enable optimizations. The patch also includes folding of previously missing saturation patterns so that IR emits the same machine instructions as the intrinsics. Patch by tkrupa Differential Revision: https://reviews.llvm.org/D44785 llvm-svn: 330322
* [X86][FMA] Remove FMA reg-reg InstRW scheduler overrides.Simon Pilgrim2018-04-194-25/+1
| | | | | | These are all already handled identically by WriteFMA. llvm-svn: 330319
* [X86][BtVer2] Remove 128-bit F16C InstRW overrides.Simon Pilgrim2018-04-191-10/+0
| | | | | | These are already handled identically by WriteCvtF2F. llvm-svn: 330318
* [mips] Guard some macro expansions properlySimon Dardis2018-04-193-20/+24
| | | | | | | | Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D45565 llvm-svn: 330315
* [AArch64][AsmParser] NFC: Cleanup parsing of scalar registers.Sander de Smalen2018-04-191-77/+69
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: - Renamed tryParseRegister to tryParseScalarRegister, which now returns an OperandMatchResultTy. - Moved matching of certain aliases into matchRegisterNameAlias. - Changed type of most 'Reg' variables to 'unsigned'. This is patch [1/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro, samparker Reviewed By: samparker Subscribers: samparker, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45687 llvm-svn: 330311
* [X86] Scrub scheduling information for MUL/IMUL on Intel CPUs.Craig Topper2018-04-195-35/+81
| | | | | | This removes a bunch of unnecessary InstRW overrides. It also cleans up the missing information from the Sandy Bridge model. Other fixes to other models. llvm-svn: 330308
* Fix data race in X86FloatingPoint.cpp ASSERT_SORTEDBob Haarman2018-04-181-7/+8
| | | | | | | | | | | | | | | | | | | | | Summary: ASSERT_SORTED checks if a table is sorted, and uses a boolean to prevent the check from being run again if it was earlier determined that the table is in fact sorted. Unsynchronized reads and writes of that boolean triggered ThreadSanitizer's data race detection. This change rewrites the code to use std::atomic<bool> instead. Fixes PR36922. Reviewers: rnk Reviewed By: rnk Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D45742 llvm-svn: 330301
* [X86] Correct the Defs, Uses, hasSideEffects, mayLoad, mayStore for XCHG and ↵Craig Topper2018-04-183-35/+52
| | | | | | | | XADD instructions. I don't think we emit any of these from codegen except for using XCHG16ar as 2 byte NOP. llvm-svn: 330298
* [NVPTX, CUDA] Added support for m8n32k16 and m32n8k16 variants of wmma ↵Artem Belevich2018-04-184-17/+85
| | | | | | | | | | instructions. The new instructions were added added for sm_70+ GPUs in CUDA-9.1. Differential Revision: https://reviews.llvm.org/D45068 llvm-svn: 330296
* [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bitsAlex Bradbury2018-04-181-2/+3
| | | | | | | These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293
* [X86] Fix the Uses/Defs,mayLoad,mayStore,hasSideEffects flags for the ↵Craig Topper2018-04-181-6/+13
| | | | | | | | CMPXCHG instructions. The compiler only emits the locked version of these which use different instruction definitions. The versions fixed here are only used by the assembler/disassembler. llvm-svn: 330287
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-189-266/+49
| | | | | | | | | Reverts rL330224, while issues with the C extension and missed common subexpression elimination opportunities are addressed. Neither of these issues are visible in current RISC-V backend unit tests, which clearly need expanding. llvm-svn: 330281
* [Power9]Legalize and emit code for converting Unsigned HWord/Char to ↵Lei Huang2018-04-181-0/+8
| | | | | | | | | | | | | | | | Quad-Precision Legalize and emit code for converting unsigned HWord/Char to QP: xscvsdqp xscvudqp Only covering patterns for unsigned forms cause we don't have part-word sign-extending integer loads into VSX registers. Differential Revision: https://reviews.llvm.org/D45494 llvm-svn: 330278
* [AArch64] Add isel pattern for v8i8->v2f32 NVCASTs.Amara Emerson2018-04-181-0/+1
| | | | | | rdar://39454635 llvm-svn: 330276
* [Power9]Legalize and emit code for converting (Un)Signed Word to Quad-PrecisionLei Huang2018-04-181-1/+10
| | | | | | | | | | | Legalize and emit code for converting (Un)Signed Word to quad-precision via: xscvsdqp xscvudqp Differential Revision: https://reviews.llvm.org/D45389 llvm-svn: 330273
* [DEBUG] Initial adaptation of NVPTX target for debug info emission.Alexey Bataev2018-04-1811-273/+207
| | | | | | | | | | | | | | | Summary: Patch adds initial emission of the debug info for NVPTX target. Currently, only .file and .loc directives are emitted, everything else is commented out to not break the compilation of Cuda. Reviewers: echristo, jlebar, tra, jholewinski Subscribers: mgorny, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41827 llvm-svn: 330271
* [x86] Switch EFLAGS copy lowering to use reg-reg form of testing forChandler Carruth2018-04-181-1/+1
| | | | | | | | | | | | | | | | a zero register. Previously I tried this and saw LLVM unable to transform this to fold with memory operands such as spill slot rematerialization. However, it clearly works as shown in this patch. We turn these into `cmpb $0, <mem>` when useful for folding a memory operand without issue. This form has no disadvantage compared to `testb $-1, <mem>`. So overall, this is likely no worse and may be slightly smaller in some cases due to the `testb %reg, %reg` form. Differential Revision: https://reviews.llvm.org/D45475 llvm-svn: 330269
* [x86] Fix PR37100 by teaching the EFLAGS copy lowering to rewrite usesChandler Carruth2018-04-181-82/+125
| | | | | | | | | | | | | | | | | | | | | | across basic blocks in the limited cases where it is very straight forward to do so. This will also be useful for other places where we do some limited EFLAGS propagation across CFG edges and need to handle copy rewrites afterward. I think this is rapidly approaching the maximum we can and should be doing here. Everything else begins to require either heroic analysis to prove how to do PHI insertion manually, or somehow managing arbitrary PHI-ing of EFLAGS with general PHI insertion. Neither of these seem at all promising so if those cases come up, we'll almost certainly need to rewrite the parts of LLVM that produce those patterns. We do now require dominator trees in order to reliably diagnose patterns that would require PHI nodes. This is a bit unfortunate but it seems better than the completely mysterious crash we would get otherwise. Differential Revision: https://reviews.llvm.org/D45673 llvm-svn: 330264
* [AMDGPU] Fix issues for backend divergence trackingDavid Stuttard2018-04-181-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A change to use divergence analysis in the AMDGPU backend was getting formal arguments incorrect (not tagged as divergent) unless they were VGPR0, VGPR1 or VGPR2 For graphics shaders it is possible to have more than these passed in as VGPR Modified the checking code to check for any VGPR registers passed in as formal arguments. Also, some intrinsics that are sources of divergence may have been lowered during instruction selection and are missed on subsequent calls to isSDNodeSourceOfDivergence - added the relevant AMDGPUISD checks as well. Finally, the FunctionLoweringInfo tracks virtual registers that are live across basic block boundaries. This is used to check for divergence of CopyFromRegister registers using the DivergenceAnalysis analysis. For multiple blocks the lazily evaluated inverted map VirtReg2Value was not cleared when the ValueMap map was. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45372 Change-Id: I112f3bd6dfe0f62e63ce9b43b893982778e4bee3 llvm-svn: 330257
* [X86][Broadwell] Remove some unnecessary InstRW overrides and add some FIXMEs.Craig Topper2018-04-181-43/+8
| | | | llvm-svn: 330241
* [X86] Give CMOV 2 cycle latency on SLM.Craig Topper2018-04-181-1/+1
| | | | llvm-svn: 330239
* [X86] Don't crash on bad operand modifiers in inline assemblyCraig Topper2018-04-181-0/+6
| | | | | | | | | | | | | | Summary: Previously if a modifer was placed on a non-GPR register class we would hit an assert or crash. Reviewers: echristo Reviewed By: echristo Subscribers: eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D45751 llvm-svn: 330238
* [AMDGPU] Enabled v2.16 literals for VOP3PStanislav Mekhanoshin2018-04-172-8/+19
| | | | | | | | Literal encoding needs op_sel_hi to select low 16 bit in this case. Differential Revision: https://reviews.llvm.org/D45745 llvm-svn: 330230
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-179-49/+266
| | | | | | | | | | | | | | The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. Additionally, PseudoLI instructions are emitted during codegen. The actual expansion to real instructions is performed during MI to MC lowering and is similar to the expansion performed by the GNU Assembler. Differential Revision: https://reviews.llvm.org/D41949 Patch by Mario Werner. llvm-svn: 330224
* [XRay] Typed event logging intrinsicKeith Wyss2018-04-173-352/+912
| | | | | | | | | | | | | | | | | | | | | Summary: Add an LLVM intrinsic for type discriminated event logging with XRay. Similar to the existing intrinsic for custom events, but also accepts a type tag argument to allow plugins to be aware of different types and semantically interpret logged events they know about without choking on those they don't. Relies on a symbol defined in compiler-rt patch D43668. I may wait to submit before I can see demo everything working together including a still to come clang patch. Reviewers: dberris, pelikan, eizan, rSerge, timshen Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45633 llvm-svn: 330219
* [WebAssembly] Add an assertion for an invalid CFGHeejin Ahn2018-04-171-0/+3
| | | | | | | | | | | | | | | Summary: It was not easy to provide a test case for D45648 (rL330079) because the bug didn't manifest itself in the set of currently valid IRs. Added an assertion to check this faster, thanks to @dblaikie's suggestion. Reviewers: dblaikie Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits, dblaikie Differential Revision: https://reviews.llvm.org/D45711 llvm-svn: 330217
* [WebAssembly] Teach fast-isel to gracefully recover from illegal return types.Dan Gohman2018-04-171-2/+6
| | | | | | Fixes PR36564. llvm-svn: 330215
* [X86] Add separate scheduling class for PSADBW instruction.Craig Topper2018-04-1713-22/+18
| | | | llvm-svn: 330204
* [X86] Remove unnecessary InstRW overrides. Add somes FIXMEs/TODOs.Craig Topper2018-04-175-98/+17
| | | | llvm-svn: 330203
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