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| author | Simon Dardis <simon.dardis@mips.com> | 2018-04-19 09:45:04 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-04-19 09:45:04 +0000 |
| commit | fdc052686cb9dd52f5a52bf72eedbd5a58fdf08b (patch) | |
| tree | f2785d5e0ea58cf88e865261246073b6be89ecae /llvm/lib/Target | |
| parent | 5976f30821483361c19ac3b2ad927f5fb8de2e48 (diff) | |
| download | bcm5719-llvm-fdc052686cb9dd52f5a52bf72eedbd5a58fdf08b.tar.gz bcm5719-llvm-fdc052686cb9dd52f5a52bf72eedbd5a58fdf08b.zip | |
[mips] Guard some macro expansions properly
Reviewers: atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D45565
llvm-svn: 330315
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 26 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 12 |
3 files changed, 24 insertions, 20 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 5ab3e9b4a9a..150af029f38 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -1202,28 +1202,32 @@ let Predicates = [InMicroMips] in { (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>; def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>; - defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>; + defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>, ISA_MICROMIPS; - defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>; + defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>, ISA_MICROMIPS; - defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>; + defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>, ISA_MICROMIPS; - defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>; + defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>, ISA_MICROMIPS; - defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi_MM>; + defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi_MM>, ISA_MICROMIPS; - defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi_MM>; + defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi_MM>, ISA_MICROMIPS; - defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>; + defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>, ISA_MICROMIPS; def : MipsInstAlias<"not $rt, $rs", - (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; + (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, + ISA_MICROMIPS; def : MipsInstAlias<"not $rt", - (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>; + (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>, + ISA_MICROMIPS; def : MipsInstAlias<"bnez $rs,$offset", - (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; + (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>, + ISA_MICROMIPS; def : MipsInstAlias<"beqz $rs,$offset", - (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; + (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>, + ISA_MICROMIPS; def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, ISA_MIPS32R2_NOT_32R6_64R6; def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 828dd4f5422..49226f19b80 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -792,13 +792,13 @@ let AdditionalPredicates = [NotInMicroMips] in { 0>, ISA_MIPS3; defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi64, GPR64Opnd, imm64>, - GPR_64; + ISA_MIPS3, GPR_64; defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi64, GPR64Opnd, imm64>, - GPR_64; + ISA_MIPS3, GPR_64; defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi64, GPR64Opnd, imm64>, - GPR_64; + ISA_MIPS3, GPR_64; } let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"dneg $rt, $rs", diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index cdbceebb21c..451cbccf9b0 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -2555,17 +2555,17 @@ let AdditionalPredicates = [NotInMicroMips] in { defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>, ISA_MIPS1_NOT_32R6_64R6; - defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>; + defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>, ISA_MIPS1; - defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi>, GPR_32; + defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi>, ISA_MIPS1, GPR_32; - defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi>, GPR_32; + defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi>, ISA_MIPS1, GPR_32; - defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi>, GPR_32; + defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi>, ISA_MIPS1, GPR_32; - defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>, GPR_32; + defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>, ISA_MIPS1, GPR_32; - defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>, GPR_32; + defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>, ISA_MIPS1, GPR_32; } def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>; def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>; |
